Add Vitis CI
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abejgonzalez
parent
dcb64c0271
commit
c0d346aa8a
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#!/usr/bin/env python3
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import sys
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from fabric.api import *
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from ci_variables import ci_workdir
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def run_linux_poweroff_vitis():
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""" Runs Base Vitis Build """
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# assumptions:
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# - machine-launch-script requirements are already installed (i.e. conda env is already active)
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# - XILINX_VITIS, XILINX_XRT, XILINX_VIVADO are setup (in env / LD_LIBRARY_PATH / path / etc)
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# - RISCV toolchain is already installed
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# repo should already be checked out
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# HACK: take the RISC-V toolchain prebuilt
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with prefix(f'source /scratch/abejgonza/chipyard-work/chipyard/env-riscv-tools.sh && cd {ci_workdir}'):
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run("./build-setup.sh --skip-toolchain --skip-validate")
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with prefix('source sourceme-f1-manager.sh'):
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# avoid logging excessive amounts to prevent GH-A masking secrets (which slows down log output)
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with prefix('cd sw/firesim-software'):
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run("./init-submodules.sh")
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# build outputs.yaml (use this workload since firemarshal can guestmount)
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with settings(warn_only=True):
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rc = run("./marshal -v build test/outputs.yaml &> outputs.full.log").return_code
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if rc != 0:
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run("cat outputs.full.log")
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raise Exception("Building test/outputs.yaml failed to run")
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run("./marshal -v install test/outputs.yaml")
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def run_w_timeout(workload_path, workload, timeout):
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log_tail_length = 100
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rc = 0
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with settings(warn_only=True):
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# avoid logging excessive amounts to prevent GH-A masking secrets (which slows down log output)
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# pty=False needed to avoid issues with screen -ls stalling in fabric
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rc = run(f"timeout {timeout} {workload_path}/run-workload.sh {workload_path}/config_runtime.yaml {workload_path}/config_hwdb.yaml {workload_path}/config_build_recipes.yaml &> {workload}.log", pty=False).return_code
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print(f" Printing last {log_tail_length} lines of log. See {workload}.log for full info.")
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run(f"tail -n {log_tail_length} {workload}.log")
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# This is a janky solution to the fact the manager does not
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# return a non-zero exit code or some sort of result summary.
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# The expectation here is that the PR author will manually
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# check these output files for correctness until it can be
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# done programmatically..
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print(f"Printing last {log_tail_length} lines of all output files. See results-workload for more info.")
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run(f"""cd deploy/results-workload/ && LAST_DIR=$(ls | tail -n1) && if [ -d "$LAST_DIR" ]; then tail -n{log_tail_length} $LAST_DIR/*/*; fi""")
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run(f"firesim terminaterunfarm -q -c {workload_path}/config_runtime.yaml -a {workload_path}/config_hwdb.yaml -r {workload_path}/config_build_recipes.yaml")
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if rc != 0:
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print(f"Workload {workload} failed.")
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sys.exit(rc)
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else:
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print(f"Workload {workload} successful.")
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run_w_timeout(f"{ci_workdir}/.github/scripts/vitis-test", "linux-poweroff-singlenode", "30m")
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if __name__ == "__main__":
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execute(run_linux_poweroff_vitis, hosts=["localhost"])
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@ -0,0 +1,8 @@
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vitis-test:
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DESIGN: FireSim
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TARGET_CONFIG: FireSimRocketConfig
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PLATFORM_CONFIG: BaseVitisConfig
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deploy_triplet: null
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post_build_hook: null
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metasim_customruntimeconfig: null
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bit_builder_recipe: bit-builder-recipes/vitis.yaml
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@ -0,0 +1,4 @@
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vitis-test:
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xclbin: /scratch/buildbot/prebuilt-xclbins/firesim.xclbin
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deploy_triplet_override: FireSim-FireSimRocketConfig-BaseVitisConfig
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custom_runtime_config: null
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@ -0,0 +1,52 @@
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run_farm:
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base_recipe: run-farm-recipes/externally_provisioned.yaml
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recipe_arg_overrides:
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default_platform: VitisInstanceDeployManager
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default_simulation_dir: /scratch/buildbot
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run_farm_hosts_to_use:
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- localhost: four_fpgas_spec
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run_farm_host_specs:
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- four_fpgas_spec:
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num_fpgas: 4
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num_metasims: 0
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use_for_switch_only: false
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metasimulation:
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metasimulation_enabled: false
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metasimulation_host_simulator: verilator
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metasimulation_only_plusargs: "+fesvr-step-size=128 +dramsim +max-cycles=100000000"
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metasimulation_only_vcs_plusargs: "+vcs+initreg+0 +vcs+initmem+0"
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target_config:
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topology: no_net_config
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no_net_num_nodes: 1
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link_latency: 6405
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switching_latency: 10
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net_bandwidth: 200
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profile_interval: -1
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default_hw_config: vitis-test
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plusarg_passthrough: ""
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tracing:
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enable: no
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output_format: 0
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selector: 1
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start: 0
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end: -1
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autocounter:
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read_rate: 0
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workload:
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workload_name: outputs.json
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terminate_on_completion: no
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suffix_tag: null
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host_debug:
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zero_out_dram: no
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disable_synth_asserts: no
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synth_print:
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start: 0
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end: -1
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cycle_prefix: yes
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@ -0,0 +1,9 @@
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#!/usr/bin/env bash
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trap "exit" INT
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set -e
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set -o pipefail
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firesim launchrunfarm -c $1 -a $2 -r $3
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firesim infrasetup -c $1 -a $2 -r $3
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firesim runworkload -c $1 -a $2 -r $3
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@ -222,6 +222,17 @@ jobs:
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- name: Run linux-poweroff test w/ externally provisioned (AWS EC2) run farm
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run: .github/scripts/run-linux-poweroff-externally-provisioned.py
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run-basic-linux-poweroff-vitis:
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if: contains(github.event.pull_request.labels.*.name, 'ci:fpga-deploy')
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name: run-basic-linux-poweroff-vitis
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runs-on: local-fpga
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env:
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TERM: xterm-256-color
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steps:
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- uses: actions/checkout@v2
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- name: Run simple linux poweroff test w/ vitis
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run: .github/scripts/run-linux-poweroff-vitis.py
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documentation-check:
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name: documentation-check
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needs: change-filters
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@ -507,9 +507,9 @@ class VitisBitBuilder(BitBuilder):
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results_build_dir = """{}/""".format(local_results_dir)
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hwdb_entry = hwdb_entry_name + ":\n"
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hwdb_entry += " xclbin: " + xclbin_path + "\n"
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hwdb_entry += " deploy_triplet_override: null\n"
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hwdb_entry += " custom_runtime_config: null\n"
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hwdb_entry += " xclbin: " + xclbin_path + "\n"
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hwdb_entry += f" deploy_triplet_override: {self.build_config.get_chisel_triplet()}\n"
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hwdb_entry += " custom_runtime_config: null\n"
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message_title = "FireSim FPGA Build Completed"
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message_body = "Your bitstream has been created!\nAdd\n\n" + hwdb_entry + "\nto your config_hwdb.ini to use this hardware configuration."
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@ -342,7 +342,10 @@ class FireSimServerNode(FireSimNode):
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run(f"sudo mount -o loop {img} {mnt}")
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else:
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run(f"""screen -S guestmount-wait -dm bash -c "guestmount --pid-file {tmp_dir}/guestmount.pid -a {img} -m /dev/sda {mnt}; while true; do sleep 1; done;" """, pty=False)
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run(f"""while [ ! "$(ls -A {mnt})" ]; do echo "Waiting for mount to finish"; sleep 1; done""")
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try:
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run(f"""while [ ! "$(ls -A {mnt})" ]; do echo "Waiting for mount to finish"; sleep 1; done""", timeout=60*10)
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except CommandTimeout:
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umount(mnt, tmp_dir)
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def umount(mnt: str, tmp_dir: str) -> None:
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if has_sudo():
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@ -61,10 +61,3 @@ prj/ -- root of generated vivado project
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This project can be re-opened interactively using
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cd $BUILD/vivado/vpl/
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vivado -source openprj.tcl
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# For Abe
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- I put one built bitstream under /scratch/biancolin/xclbins. You should be able to rebuild the default driver
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by typing `make vitis` under sim/.
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- Scripts to reflash FPGAs second stage shells and reset can be found under scripts/
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@ -279,7 +279,7 @@ set -o pipefail
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expect \
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dtc \
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verilator==4.034 \
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screen \
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screen \
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)
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# python packages
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@ -26,8 +26,8 @@ TARGET_PROJECT ?= firesim
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# that submodules firesim or source sim/Makefrag directly
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TARGET_PROJECT_MAKEFRAG ?= $(firesim_base_dir)/src/main/makefrag/$(TARGET_PROJECT)/Makefrag
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# The host-platform type (currently only f1 supported)
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PLATFORM ?= vitis
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# The host-platform type (currently only f1, vitis supported)
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PLATFORM ?= f1
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ifdef FIRESIM_STANDALONE
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@ -17,7 +17,7 @@ class AXI42NastiIdentityModule(params: AXI4BundleParameters)(implicit p: Paramet
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AXI4NastiAssigner.toNasti(io.nasti, io.axi4)
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}
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class Nasti2AXI4IdentityModule(params: AXI4BundleParameters)(implicit p: Parameters)
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class Nasti2AXI4IdentityModule(params: AXI4BundleParameters)(implicit p: Parameters)
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extends RawModule with InlineInstance {
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val io = IO(new Bundle {
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val axi4 = new AXI4Bundle(params)
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@ -38,7 +38,7 @@ class Nasti2AXI4Monitor(params: AXI4BundleParameters)(implicit p: Parameters)
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/**
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* THe Nasti -> AXI4 implies here that all methods of this object accept
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* NastiIO as their primary argument. NB: the Nasti bundle may be mastered or be mastered
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* NastiIO as their primary argument. NB: the Nasti bundle may be mastered or be mastered
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* by the resulting AXI4.
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*
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*/
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@ -47,7 +47,7 @@ object Nasti2AXI4 {
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def toMonitor(nastiIO: NastiIO)(implicit p: Parameters): AXI4Bundle = {
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val axi4Params = AXI4BundleParameters(nastiIO.ar.bits.addr.getWidth,
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nastiIO.r.bits.data.getWidth,
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nastiIO.ar.bits.id .getWidth)
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nastiIO.ar.bits.id.getWidth)
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val conv = Module(new Nasti2AXI4Monitor(axi4Params))
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conv.io.nasti := nastiIO
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conv.io.axi4
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@ -56,7 +56,7 @@ object Nasti2AXI4 {
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/**
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* THe AXI4 -> Nasti implies here that all methods of this object accept
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* AXI4 as their primary argument.
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* AXI4 as their primary argument.
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*
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*/
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object AXI42Nasti {
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@ -8,13 +8,12 @@ DESIGN ?= FireSim
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# These guide chisel elaboration of the target design specified above.
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# See src/main/scala/SimConfigs.scala
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TARGET_CONFIG_PACKAGE ?= firesim.firesim
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#TARGET_CONFIG ?= FireSimNoMemPortConfig
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TARGET_CONFIG ?= FireSimRocketConfig
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# These guide chisel elaboration of simulation components by MIDAS, including models and widgets.
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# See src/main/scala/SimConfigs.scala
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PLATFORM_CONFIG_PACKAGE ?= firesim.firesim
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PLATFORM_CONFIG ?= BaseVitisConfig
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PLATFORM_CONFIG ?= BaseF1Config
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name_tuple := $(DESIGN)-$(TARGET_CONFIG)-$(PLATFORM_CONFIG)
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GENERATED_DIR := $(firesim_base_dir)/generated-src/$(PLATFORM)/$(name_tuple)
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@ -197,8 +197,6 @@ $(vitis): export LDFLAGS := $(LDFLAGS) $(common_ld_flags) -Wl,-rpath='$$$$ORIGIN
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$(vitis): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h)
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mkdir -p $(OUTPUT_DIR)/build
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cp $(header) $(OUTPUT_DIR)/build/
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# The manager expects to find the default conf in output/ by this name
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cp -f $(GENERATED_DIR)/$(CONF_NAME) $(OUTPUT_DIR)/runtime.conf
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$(MAKE) -C $(simif_dir) vitis PLATFORM=vitis DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
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GEN_DIR=$(OUTPUT_DIR)/build OUT_DIR=$(OUTPUT_DIR) DRIVER="$(DRIVER_CC)" \
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TOP_DIR=$(chipyard_dir)
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