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Improve makefile variable naming

This commit is contained in:
David Biancolin 2018-08-27 03:22:37 +00:00
parent 29fe4d569a
commit 30d4d4aef1
3 changed files with 19 additions and 19 deletions
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23
sim/Makefile
View File

@ -2,19 +2,18 @@
# Parameters #
##################
# Multiple target-projects co-exist in firesim, their sources exist in:
# src/main/{cc, scala, makefrag}/<project-name>
# Multiple target-projects, each with it's own chisel generator, co-exist in firesim.
# Their sources exist in:
# src/main/{cc, scala, makefrag}/<target-project-name>
#
# Currently these projects are:
# firesim: the default, rocket-chip-based target designs
# midasexamples: simple chisel designs, demonstrating how to build midas-style simulators
ROOT_PROJECT ?= firesim
# firesim: the default, rocket-chip-based target-designs
# midasexamples: simple chisel designs demonstrating how to build midas-style simulators
TARGET_PROJECT ?= firesim
# Users can override this to point at a makefrag defined in a parent project that submodules firesim
ROOT_PROJECT_MAKEFRAG ?= src/main/makefrag/$(ROOT_PROJECT)/Makefrag
# The host-platform type.
PLATFORM := f1
# Users can override this to point at a makefrag defined in a parent project
# that submodules firesim or source sim/Makefrag directly
TARGET_PROJECT_MAKEFRAG ?= src/main/makefrag/$(TARGET_PROJECT)/Makefrag
default: compile
@ -35,8 +34,10 @@ $(firesim_base_dir)/firrtl.timestamp: $(shell find $(firesim_base_dir)/firrtl/$(
cd $(firesim_base_dir)/firrtl && $(SBT) $(SBT_FLAGS) publishLocal
touch $@
PLATFORM := f1
# Include target-specific sources and input generation recipes
include $(ROOT_PROJECT_MAKEFRAG)
include $(TARGET_PROJECT_MAKEFRAG)
verilog: $(VERILOG)
compile: $(VERILOG)

13
sim/src/main/makefrag/firesim/Makefrag
View File

@ -1,17 +1,17 @@
# These point at the main class of the target's Chisel generator
PROJECT ?= firesim.firesim
DESIGN_PACKAGE ?= firesim.firesim
DESIGN ?= FireSim
# DESIGN ?= FireBoom
# These guide chisel elaboration of the target design specified above.
# See src/main/scala/SimConfigs.scala
TARGET_PROJECT ?= firesim.firesim
TARGET_CONFIG_PACKAGE ?= firesim.firesim
TARGET_CONFIG ?= FireSimRocketChipConfig
# TARGET_CONFIG ?= FireSimBoomConfig
# These guide chisel elaboration of simulation components by MIDAS, including models and widgets.
# See src/main/scala/SimConfigs.scala
PLATFORM_PROJECT ?= firesim.firesim
PLATFORM_CONFIG_PACKAGE ?= firesim.firesim
PLATFORM_CONFIG ?= FireSimConfig
base_dir = $(abspath .)
@ -32,13 +32,12 @@ submodules = . midas firrtl \
src_path = src/main/scala
chisel_srcs = $(foreach submodule,$(submodules),$(shell find $(base_dir)/$(submodule)/$(src_path) -name "*.scala"))
common_chisel_args = $(patsubst $(base_dir)/%,%,$(GENERATED_DIR)) $(PROJECT) $(DESIGN) $(TARGET_PROJECT) $(TARGET_CONFIG) $(PLATFORM_PROJECT) $(PLATFORM_CONFIG)
common_chisel_args = $(patsubst $(base_dir)/%,%,$(GENERATED_DIR)) $(DESIGN_PACKAGE) $(DESIGN) $(TARGET_CONFIG_PACKAGE) $(TARGET_CONFIG) $(PLATFORM_CONFIG_PACKAGE) $(PLATFORM_CONFIG)
$(VERILOG) $(HEADER): $(chisel_srcs) $(timestamps)
mkdir -p $(@D)
$(SBT) $(SBT_FLAGS) \
"runMain $(PROJECT).FireSimGenerator $(if $(STROBER),strober,midas) $(common_chisel_args)"
"runMain $(DESIGN_PACKAGE).FireSimGenerator $(if $(STROBER),strober,midas) $(common_chisel_args)"
##########################
# Driver Sources & Flags #
@ -61,7 +60,7 @@ CONF_NAME ?= runtime.conf
conf:
mkdir -p $(GENERATED_DIR)
$(SBT) $(SBT_FLAGS) \
"runMain $(PROJECT).FireSimRuntimeConfGenerator $(CONF_NAME) $(common_chisel_args)"
"runMain $(DESIGN_PACKAGE).FireSimRuntimeConfGenerator $(CONF_NAME) $(common_chisel_args)"
############################################
# Midas-Level Simulation Execution Recipes #

2
sim/src/test/scala/midasexamples/TutorialSuite.scala
View File

@ -12,7 +12,7 @@ abstract class TutorialSuite(
) extends TestSuiteCommon with GeneratorUtils {
val args = Seq(s"+tracelen=$tracelen") ++ simulationArgs
val commonMakeArgs = Seq(s"ROOT_PROJECT=midasexamples", s"DESIGN=$targetName")
val commonMakeArgs = Seq(s"TARGET_PROJECT=midasexamples", s"DESIGN=$targetName")
val targetTuple = targetName
//implicit val p = (platform match {