Split `target-agnostic.mk` into multiple files (#1353)
The `target-agnostic.mk` file is a monolith that performs too many tasks at once. This PR splits it into multiple independent files to delimit the different tasks. Also moves definitions closer together for clarity. Existing external users of `target-agnostic.mk` can include the individual splits they are interested in.
This commit is contained in:
Nandor Licker
GitHub
parent
430156a733
commit
7ccc6cd37f
113
sim/Makefile
113
sim/Makefile
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@ -1,13 +1,16 @@
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# See LICENSE for license details.
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.PHONY: default
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default: compile
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ifndef FIRESIM_ENV_SOURCED
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$(error You must source sourceme-f1-manager.sh or env.sh to use this Makefile)
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endif
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firesim_base_dir := $(abspath .)
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.PHONY: default
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default: compile
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# Set up environment variables pointing to Chipyard and SBT.
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include make/chipyard.mk
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##################
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# Parameters #
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@ -29,84 +32,40 @@ TARGET_PROJECT_MAKEFRAG ?= $(firesim_base_dir)/src/main/makefrag/$(TARGET_PROJEC
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# The host-platform type (currently only f1, vitis supported)
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PLATFORM ?= f1
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ifdef FIRESIM_STANDALONE
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base_dir := $(firesim_base_dir)
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chipyard_dir := $(abspath ..)/target-design/chipyard
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rocketchip_dir := $(chipyard_dir)/generators/rocket-chip
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# Scala invocation options
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JVM_MEMORY ?= 16G
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SCALA_VERSION ?= 2.12.10
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# Disable the SBT supershell as interacts poorly with scalatest output and breaks
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# the runtime config generator.
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export JAVA_TOOL_OPTIONS ?= -Xmx$(JVM_MEMORY) -Xss8M -Dsbt.supershell=false -Djava.io.tmpdir=$(base_dir)/.java_tmp
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sbt_sources = $(shell find -L $(base_dir) -name target -prune -o -iname "*.sbt" -print 2> /dev/null)
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SCALA_BUILDTOOL_DEPS ?= $(sbt_sources)
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SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/project/target/active.json
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ifdef ENABLE_SBT_THIN_CLIENT
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override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP)
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# enabling speeds up sbt loading
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SBT_CLIENT_FLAG = --client
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endif
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# Use java -jar approach by default so that SBT thin-client sees the JAVA flags
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# Workaround for behavior reported here: https://github.com/sbt/sbt/issues/6468
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SBT_BIN ?= java -jar $(rocketchip_dir)/sbt-launch.jar
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SBT = $(SBT_BIN) $(SBT_CLIENT_FLAG)
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define run_scala_main
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cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)"
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endef
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##############################################################################
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# SBT Server Setup (start server / rebuild proj. defs. if SBT_SOURCES change)
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##############################################################################
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$(SBT_THIN_CLIENT_TIMESTAMP): $(SBT_SOURCES)
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ifneq (,$(wildcard $(SBT_THIN_CLIENT_TIMESTAMP)))
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cd $(base_dir) && $(SBT) "reload"
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touch $@
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else
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cd $(base_dir) && $(SBT) "exit"
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endif
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.PHONY: shutdown-sbt-server
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shutdown-sbt-server:
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cd $(base_dir) && $(SBT) "shutdown"
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.PHONY: start-sbt-server
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start-sbt-server:
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cd $(base_dir) && $(SBT) "exit"
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else
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# Chipyard make variables
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base_dir := $(abspath ../../..)
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sim_dir := $(firesim_base_dir)
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chipyard_dir := $(base_dir)
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include $(base_dir)/variables.mk
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include $(base_dir)/common.mk
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endif
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####################
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# Target Setup #
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####################
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# Include target-specific sources and input generation recipes
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include $(TARGET_PROJECT_MAKEFRAG)
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# Phony targets for launching the sbt shell and running scalatests
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SBT_COMMAND ?= shell
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SBT_NON_THIN ?= $(subst $(SBT_CLIENT_FLAG),,$(SBT))
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.PHONY: sbt
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sbt:
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cd $(base_dir) && $(SBT_NON_THIN) ";project $(firesim_sbt_project); $(SBT_COMMAND)"
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.PHONY: test
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test:
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cd $(base_dir) && $(SBT_NON_THIN) ";project $(firesim_sbt_project); test"
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.PHONY: testOnly
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testOnly:
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cd $(base_dir) && $(SBT_NON_THIN) ";project $(firesim_sbt_project); testOnly $(SCALA_TEST)"
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# All target-agnostic firesim recipes are defined here
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include target-agnostic.mk
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include make/config.mk
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include make/library.mk
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include make/goldengate.mk
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include make/fpga.mk
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include make/verilator.mk
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include make/vcs.mk
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include make/driver.mk
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include make/unittest.mk
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include make/scala.mk
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#########################
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# Cleaning Recipes #
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#########################
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.PHONY: mostlyclean
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mostlyclean:
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rm -rf $(verilator) $(verilator_debug) $(vcs) $(vcs_debug) $($(PLATFORM)) $(OUTPUT_DIR)
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.PHONY: clean
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clean:
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rm -rf $(GENERATED_DIR) $(OUTPUT_DIR)
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.PHONY: veryclean
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veryclean:
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rm -rf generated-src output
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# Remove all implicit suffix rules; This improves make performance substantially as it no longer
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# attempts to resolve implicit rules on 1000+ scala files.
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.SUFFIXES:
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@ -0,0 +1,84 @@
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# See LICENSE for license details.
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ifdef FIRESIM_STANDALONE
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base_dir := $(firesim_base_dir)
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chipyard_dir := $(abspath ..)/target-design/chipyard
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rocketchip_dir := $(chipyard_dir)/generators/rocket-chip
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# Scala invocation options
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JVM_MEMORY ?= 16G
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SCALA_VERSION ?= 2.12.10
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# Disable the SBT supershell as interacts poorly with scalatest output and breaks
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# the runtime config generator.
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export JAVA_TOOL_OPTIONS ?= -Xmx$(JVM_MEMORY) -Xss8M -Dsbt.supershell=false -Djava.io.tmpdir=$(base_dir)/.java_tmp
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sbt_sources = $(shell find -L $(base_dir) -name target -prune -o -iname "*.sbt" -print 2> /dev/null)
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SCALA_BUILDTOOL_DEPS ?= $(sbt_sources)
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SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/project/target/active.json
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ifdef ENABLE_SBT_THIN_CLIENT
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override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP)
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# enabling speeds up sbt loading
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SBT_CLIENT_FLAG = --client
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endif
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# Use java -jar approach by default so that SBT thin-client sees the JAVA flags
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# Workaround for behavior reported here: https://github.com/sbt/sbt/issues/6468
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SBT_BIN ?= java -jar $(rocketchip_dir)/sbt-launch.jar
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SBT = $(SBT_BIN) $(SBT_CLIENT_FLAG)
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define run_scala_main
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cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)"
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endef
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##############################################################################
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# SBT Server Setup (start server / rebuild proj. defs. if SBT_SOURCES change)
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##############################################################################
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$(SBT_THIN_CLIENT_TIMESTAMP): $(SBT_SOURCES)
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ifneq (,$(wildcard $(SBT_THIN_CLIENT_TIMESTAMP)))
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cd $(base_dir) && $(SBT) "reload"
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touch $@
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else
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cd $(base_dir) && $(SBT) "exit"
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endif
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.PHONY: shutdown-sbt-server
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shutdown-sbt-server:
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cd $(base_dir) && $(SBT) "shutdown"
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.PHONY: start-sbt-server
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start-sbt-server:
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cd $(base_dir) && $(SBT) "exit"
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else # FIRESIM_STANDALONE
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# Chipyard make variables
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base_dir := $(abspath ../../..)
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sim_dir := $(firesim_base_dir)
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chipyard_dir := $(base_dir)
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include $(base_dir)/variables.mk
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include $(base_dir)/common.mk
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endif
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ifdef FIRESIM_STANDALONE
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firesim_sbt_project := firesim
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else
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firesim_sbt_project := {file:${firesim_base_dir}/}firesim
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endif
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# Phony targets for launching the sbt shell and running scalatests
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SBT_COMMAND ?= shell
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SBT_NON_THIN ?= $(subst $(SBT_CLIENT_FLAG),,$(SBT))
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.PHONY: sbt
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sbt:
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cd $(base_dir) && $(SBT_NON_THIN) ";project $(firesim_sbt_project); $(SBT_COMMAND)"
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.PHONY: test
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test:
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cd $(base_dir) && $(SBT_NON_THIN) ";project $(firesim_sbt_project); test"
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.PHONY: testOnly
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testOnly:
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cd $(base_dir) && $(SBT_NON_THIN) ";project $(firesim_sbt_project); testOnly $(SCALA_TEST)"
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@ -0,0 +1,45 @@
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# FireSim Target Agnostic Make Fragment
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#
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# Defines make targets for:
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# - invoking Golden Gate (phony: verilog / compile)
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# - building a simulation driver (phony: f1)
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# - populating an FPGA build directory (phony: replace-rtl)
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# - generating new runtime configurations (phony: conf)
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# - compiling meta-simulators (phony: verilator, vcs, verilator-debug, vcs-debug)
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#
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# The prefix used for all Golden Gate-generated files
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BASE_FILE_NAME ?=
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# The directory into which generated verilog and headers will be dumped
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# RTL simulations will also be built here
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GENERATED_DIR ?=
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# Results from RTL simulations live here
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OUTPUT_DIR ?=
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# Root name for generated binaries
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DESIGN ?=
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# The target's FIRRTL and associated anotations; inputs to Golden Gate
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FIRRTL_FILE ?=
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ANNO_FILE ?=
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# The host config package and class string
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PLATFORM_CONFIG_PACKAGE ?= firesim.midasexamples
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PLATFORM_CONFIG ?= DefaultF1Config
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# The name of the generated runtime configuration file
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CONF_NAME ?= $(BASE_FILE_NAME).runtime.conf
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# The host platform type, currently only f1 is supported
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PLATFORM ?=
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# Driver source files
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DRIVER_CC ?=
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DRIVER_H ?=
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# Target-specific CXX and LD flags for compiling the driver and meta-simulators
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# These should be platform independent should be governed by the target-specific makefrag
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TARGET_CXX_FLAGS ?=
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TARGET_LD_FLAGS ?=
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# END MAKEFRAG INTERFACE
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@ -0,0 +1,44 @@
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# See LICENSE for license details.
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############################
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# Master Simulation Driver #
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############################
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DRIVER_CXXOPTS ?= -O2
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platforms_dir := $(abspath $(firesim_base_dir)/../platforms)
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$(PLATFORM) = $(OUTPUT_DIR)/$(DESIGN)-$(PLATFORM)
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$(PLATFORM): $($(PLATFORM))
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.PHONY: driver
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driver: $(PLATFORM)
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$(f1): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) $(DRIVER_CXXOPTS) \
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-I$(platforms_dir)/f1/aws-fpga/sdk/userspace/include
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# We will copy shared libs into same directory as driver on runhost, so add $ORIGIN to rpath
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$(f1): export LDFLAGS := $(LDFLAGS) $(common_ld_flags) -Wl,-rpath='$$$$ORIGIN' -L /usr/local/lib64 -lfpga_mgmt
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# Compile Driver
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$(f1): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h)
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mkdir -p $(OUTPUT_DIR)/build
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cp $(header) $(OUTPUT_DIR)/build/
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$(MAKE) -C $(simif_dir) f1 PLATFORM=f1 DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
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GEN_DIR=$(OUTPUT_DIR)/build OUT_DIR=$(OUTPUT_DIR) DRIVER="$(DRIVER_CC)" \
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TOP_DIR=$(chipyard_dir)
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$(vitis): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) $(DRIVER_CXXOPTS) \
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-idirafter ${CONDA_PREFIX}/include -idirafter /usr/include -idirafter $(XILINX_XRT)/include
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$(vitis): export LDFLAGS := $(LDFLAGS) $(common_ld_flags) -Wl,-rpath='$$$$ORIGIN' \
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-L${CONDA_PREFIX}/lib -Wl,-rpath-link=/usr/lib/x86_64-linux-gnu -L$(XILINX_XRT)/lib -luuid -lxrt_coreutil
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# Compile Driver
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$(vitis): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h)
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mkdir -p $(OUTPUT_DIR)/build
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cp $(header) $(OUTPUT_DIR)/build/
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$(MAKE) -C $(simif_dir) vitis PLATFORM=vitis DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
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GEN_DIR=$(OUTPUT_DIR)/build OUT_DIR=$(OUTPUT_DIR) DRIVER="$(DRIVER_CC)" \
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TOP_DIR=$(chipyard_dir)
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tags: $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h)
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ctags -R --exclude=@.ctagsignore .
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@ -0,0 +1,94 @@
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# See LICENSE for license details.
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#############################
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# FPGA Build Initialization #
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#############################
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platforms_dir := $(abspath $(firesim_base_dir)/../platforms)
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ifeq ($(PLATFORM), vitis)
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board_dir := $(platforms_dir)/vitis
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else
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board_dir := $(platforms_dir)/f1/aws-fpga/hdk/cl/developer_designs
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endif
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fpga_work_dir := $(board_dir)/cl_$(name_tuple)
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fpga_build_dir := $(fpga_work_dir)/build
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verif_dir := $(fpga_work_dir)/verif
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repo_state := $(fpga_work_dir)/design/repo_state
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fpga_driver_dir:= $(fpga_work_dir)/driver
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# Enumerates the subset of generated files that must be copied over for FPGA compilation
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fpga_delivery_files = $(addprefix $(fpga_work_dir)/design/$(BASE_FILE_NAME), \
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.sv .defines.vh \
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.synthesis.xdc .implementation.xdc)
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# Files used to run FPGA-level metasimulation
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fpga_sim_delivery_files = $(addprefix $(fpga_driver_dir)/$(BASE_FILE_NAME), .runtime.conf) \
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$(fpga_driver_dir)/$(DESIGN)-$(PLATFORM)
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$(fpga_work_dir)/stamp: $(shell find $(board_dir)/cl_firesim -name '*')
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mkdir -p $(driver_dir) #Could just set up in the shell project
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cp -rf $(board_dir)/cl_firesim -T $(fpga_work_dir)
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touch $@
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$(repo_state): $(simulator_verilog) $(fpga_work_dir)/stamp
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$(firesim_base_dir)/../scripts/repo_state_summary.sh > $(repo_state)
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$(fpga_work_dir)/design/$(BASE_FILE_NAME)%: $(simulator_verilog) $(fpga_work_dir)/stamp
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cp -f $(GENERATED_DIR)/*.ipgen.tcl $(@D) || true
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cp -f $(GENERATED_DIR)/$(@F) $@
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$(fpga_driver_dir)/$(BASE_FILE_NAME)%: $(simulator_verilog) $(fpga_work_dir)/stamp
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mkdir -p $(@D)
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cp -f $(GENERATED_DIR)/$(@F) $@
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$(fpga_driver_dir)/$(DESIGN)-$(PLATFORM): $($(PLATFORM))
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cp -f $< $@
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# Goes as far as setting up the build directory without running the cad job
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# Used by the manager before passing a build to a remote machine
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replace-rtl: $(fpga_delivery_files) $(fpga_sim_delivery_files)
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.PHONY: replace-rtl
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$(firesim_base_dir)/scripts/checkpoints/$(target_sim_tuple): $(fpga_work_dir)/stamp
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mkdir -p $(@D)
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ln -sf $(fpga_build_dir)/checkpoints/to_aws $@
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# Runs a local fpga-bitstream build. Strongly consider using the manager instead.
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.PHONY: fpga
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fpga: export CL_DIR := $(fpga_work_dir)
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fpga: $(fpga_delivery_files) $(base_dir)/scripts/checkpoints/$(target_sim_tuple)
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cd $(fpga_build_dir)/scripts && ./aws_build_dcp_from_cl.sh -notify
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#############################
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# FPGA-level RTL Simulation #
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#############################
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# Run XSIM DUT
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.PHONY: xsim-dut
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xsim-dut: replace-rtl $(fpga_work_dir)/stamp
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cd $(verif_dir)/scripts && $(MAKE) C_TEST=test_firesim
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# Compile XSIM Driver #
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xsim = $(GENERATED_DIR)/$(DESIGN)-$(PLATFORM)
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$(xsim): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) -D SIMULATION_XSIM -D NO_MAIN
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$(xsim): export LDFLAGS := $(LDFLAGS) $(common_ld_flags)
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$(xsim): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h)
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$(MAKE) -C $(simif_dir) f1 PLATFORM=f1 DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
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GEN_DIR=$(GENERATED_DIR) OUT_DIR=$(GENERATED_DIR) DRIVER="$(DRIVER_CC)" \
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TOP_DIR=$(chipyard_dir)
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.PHONY: xsim
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xsim: $(xsim)
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#########################
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# Cleaning Recipes #
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#########################
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.PHONY: cleanfpga
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cleanfpga:
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rm -rf $(fpga_work_dir)
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@ -0,0 +1,58 @@
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# See LICENSE for license details.
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####################################
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# Golden Gate Invocation #
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####################################
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# Simulation memory map emitted by the MIDAS compiler
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header := $(GENERATED_DIR)/$(BASE_FILE_NAME).const.h
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# The midas-generated simulator RTL which will be baked into the FPGA shell project
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simulator_verilog := $(GENERATED_DIR)/$(BASE_FILE_NAME).sv
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# Pre-simulation-mapping annotations which includes all Bridge Annotations
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# extracted used to generate new runtime configurations.
|
||||
fame_annos := $(GENERATED_DIR)/post-bridge-extraction.json
|
||||
|
||||
.PHONY: verilog compile
|
||||
verilog: $(simulator_verilog)
|
||||
compile: $(simulator_verilog)
|
||||
|
||||
# empty recipe to help make understand multiple targets come from single recipe invocation
|
||||
# without using the new (4.3) '&:' grouped targets see https://stackoverflow.com/a/41710495
|
||||
.SECONDARY: $(simulator_verilog).intermediate
|
||||
$(simulator_verilog) $(header) $(fame_annos): $(simulator_verilog).intermediate ;
|
||||
|
||||
# Disable FIRRTL 1.4 deduplication because it creates multiple failures
|
||||
# Run the 1.3 version instead (checked-in). If dedup must be completely disabled,
|
||||
# pass --no-legacy-dedup as well
|
||||
$(simulator_verilog).intermediate: $(FIRRTL_FILE) $(ANNO_FILE) $(SCALA_BUILDTOOL_DEPS)
|
||||
$(call run_scala_main,$(firesim_sbt_project),midas.stage.GoldenGateMain,\
|
||||
-i $(FIRRTL_FILE) \
|
||||
-td $(GENERATED_DIR) \
|
||||
-faf $(ANNO_FILE) \
|
||||
-ggcp $(PLATFORM_CONFIG_PACKAGE) \
|
||||
-ggcs $(PLATFORM_CONFIG) \
|
||||
--output-filename-base $(BASE_FILE_NAME) \
|
||||
--no-dedup \
|
||||
)
|
||||
grep -sh ^ $(GENERATED_DIR)/firrtl_black_box_resource_files.f | \
|
||||
xargs cat >> $(simulator_verilog) # Append blackboxes to FPGA wrapper, if any
|
||||
|
||||
####################################
|
||||
# Runtime-Configuration Generation #
|
||||
####################################
|
||||
|
||||
# This reads in the annotations from a generated target, elaborates a
|
||||
# FASEDTimingModel if a BridgeAnnoation for one exists, and asks for user input
|
||||
# to generate a runtime configuration that is compatible with the generated
|
||||
# hardware (BridgeModule). Useful for modelling a memory system that differs from the default.
|
||||
.PHONY: conf
|
||||
conf: $(fame_annos)
|
||||
mkdir -p $(GENERATED_DIR)
|
||||
cd $(base_dir) && $(SBT) "project $(firesim_sbt_project)" "runMain midas.stage.RuntimeConfigGeneratorMain \
|
||||
-td $(GENERATED_DIR) \
|
||||
-faf $(fame_annos) \
|
||||
-ggcp $(PLATFORM_CONFIG_PACKAGE) \
|
||||
-ggcs $(PLATFORM_CONFIG) \
|
||||
-ggrc $(CONF_NAME)"
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
# See LICENSE for license details.
|
||||
|
||||
# Defined for each platform
|
||||
|
||||
simif_dir = $(firesim_base_dir)/midas/src/main/cc
|
||||
midas_h = $(shell find $(simif_dir) -name "*.h")
|
||||
midas_cc = $(shell find $(simif_dir) -name "*.cc")
|
||||
|
||||
common_cxx_flags := $(TARGET_CXX_FLAGS) -Wno-unused-variable
|
||||
common_ld_flags := $(TARGET_LD_FLAGS) -lrt
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# See LICENSE for license details.
|
||||
|
||||
#########################
|
||||
# ScalaDoc #
|
||||
#########################
|
||||
.PHONY: scaladoc
|
||||
scaladoc:
|
||||
cd $(base_dir) && $(SBT) "project {file:$(firesim_base_dir)}firesim" "unidoc"
|
||||
|
||||
#########################
|
||||
# Scalafmt #
|
||||
#########################
|
||||
|
||||
# Checks that all scala main sources under firesim SBT subprojects are formatted.
|
||||
.PHONY: scalafmtCheckAll
|
||||
scalafmtCheckAll:
|
||||
cd $(base_dir) && $(SBT) ";project {file:$(firesim_base_dir)}firesim; \
|
||||
firesim / scalafmtCheckAll; \
|
||||
firesimLib / scalafmtCheckAll; \
|
||||
midas / scalafmtCheckAll ; \
|
||||
targetutils / scalafmtCheckAll ;"
|
||||
|
||||
# Runs the code reformatter in all firesim SBT subprojects
|
||||
.PHONY: scalafmtAll
|
||||
scalafmtAll:
|
||||
cd $(base_dir) && $(SBT) ";project {file:$(firesim_base_dir)}firesim; \
|
||||
firesim / scalafmtAll; \
|
||||
firesimLib / scalafmtAll; \
|
||||
midas / scalafmtAll ; \
|
||||
targetutils / scalafmtAll ;"
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
# See LICENSE for license details.
|
||||
|
||||
#########################
|
||||
# MIDAS Unit Tests #
|
||||
#########################
|
||||
|
||||
UNITTEST_CONFIG ?= AllUnitTests
|
||||
|
||||
firesim_root_sbt_project := {file:$(firesim_base_dir)}firesim
|
||||
|
||||
rocketchip_dir := $(chipyard_dir)/generators/rocket-chip
|
||||
unittest_generated_dir := $(base_dir)/generated-src/unittests/$(UNITTEST_CONFIG)
|
||||
unittest_args = \
|
||||
BASE_DIR=$(base_dir) \
|
||||
EMUL=$(EMUL) \
|
||||
ROCKETCHIP_DIR=$(rocketchip_dir) \
|
||||
GEN_DIR=$(unittest_generated_dir) \
|
||||
SBT="$(SBT)" \
|
||||
SBT_PROJECT=$(firesim_root_sbt_project) \
|
||||
CONFIG=$(UNITTEST_CONFIG) \
|
||||
TOP_DIR=$(chipyard_dir)
|
||||
|
||||
.PHONY:compile-midas-unittests
|
||||
compile-midas-unittests: $(chisel_srcs)
|
||||
$(MAKE) -f $(simif_dir)/unittest/Makefrag $(unittest_args)
|
||||
|
||||
.PHONY:run-midas-unittests
|
||||
run-midas-unittests: $(chisel_srcs)
|
||||
$(MAKE) -f $(simif_dir)/unittest/Makefrag $@ $(unittest_args)
|
||||
|
||||
.PHONY:run-midas-unittests-debug
|
||||
run-midas-unittests-debug: $(chisel_srcs)
|
||||
$(MAKE) -f $(simif_dir)/unittest/Makefrag $@ $(unittest_args)
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
# See LICENSE for license details.
|
||||
|
||||
##############################
|
||||
# VCS MIDAS-Level Simulators #
|
||||
##############################
|
||||
|
||||
VCS_CXXOPTS ?= -O2
|
||||
|
||||
vcs = $(GENERATED_DIR)/$(DESIGN)
|
||||
vcs_debug = $(GENERATED_DIR)/$(DESIGN)-debug
|
||||
|
||||
$(vcs) $(vcs_debug): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) $(VCS_CXXOPTS) -I$(VCS_HOME)/include -D RTLSIM
|
||||
# VCS can mangle the ordering of libraries and object files at link time such
|
||||
# that some valid dependencies are pruned when --as-needed is set.
|
||||
# Conservatively set --no-as-needed in case --as-needed is defined in LDFLAGS.
|
||||
$(vcs) $(vcs_debug): export LDFLAGS := $(LDFLAGS) -Wl,--no-as-needed $(common_ld_flags) -Wl,-rpath='$$$$ORIGIN'
|
||||
|
||||
$(vcs): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h) $(simulator_verilog)
|
||||
$(MAKE) -C $(simif_dir) vcs PLATFORM=$(PLATFORM) DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
|
||||
GEN_DIR=$(GENERATED_DIR) DRIVER="$(DRIVER_CC)" TOP_DIR=$(chipyard_dir)
|
||||
|
||||
$(vcs_debug): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h) $(simulator_verilog)
|
||||
$(MAKE) -C $(simif_dir) vcs-debug PLATFORM=$(PLATFORM) DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
|
||||
GEN_DIR=$(GENERATED_DIR) DRIVER="$(DRIVER_CC)" TOP_DIR=$(chipyard_dir)
|
||||
|
||||
.PHONY: vcs vcs-debug
|
||||
vcs: $(vcs)
|
||||
vcs-debug: $(vcs_debug)
|
||||
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
# See LICENSE for license details.
|
||||
|
||||
####################################
|
||||
# Verilator MIDAS-Level Simulators #
|
||||
####################################
|
||||
|
||||
VERILATOR_CXXOPTS ?= -O0
|
||||
VERILATOR_MAKEFLAGS ?= -j8 VM_PARALLEL_BUILDS=1
|
||||
|
||||
verilator = $(GENERATED_DIR)/V$(DESIGN)
|
||||
verilator_debug = $(GENERATED_DIR)/V$(DESIGN)-debug
|
||||
|
||||
$(verilator) $(verilator_debug): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) $(VERILATOR_CXXOPTS) -D RTLSIM
|
||||
$(verilator) $(verilator_debug): export LDFLAGS := $(LDFLAGS) $(common_ld_flags) -Wl,-rpath='$$$$ORIGIN'
|
||||
|
||||
$(verilator): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h) $(simulator_verilog)
|
||||
$(MAKE) $(VERILATOR_MAKEFLAGS) -C $(simif_dir) verilator PLATFORM=$(PLATFORM) DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
|
||||
GEN_DIR=$(GENERATED_DIR) DRIVER="$(DRIVER_CC)" TOP_DIR=$(chipyard_dir) VERILATOR_FLAGS="$(EXTRA_VERILATOR_FLAGS)"
|
||||
|
||||
$(verilator_debug): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h) $(simulator_verilog)
|
||||
$(MAKE) $(VERILATOR_MAKEFLAGS) -C $(simif_dir) verilator-debug PLATFORM=$(PLATFORM) DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
|
||||
GEN_DIR=$(GENERATED_DIR) DRIVER="$(DRIVER_CC)" TOP_DIR=$(chipyard_dir) VERILATOR_FLAGS="$(EXTRA_VERILATOR_FLAGS)"
|
||||
|
||||
.PHONY: verilator verilator-debug
|
||||
verilator: $(verilator)
|
||||
verilator-debug: $(verilator_debug)
|
||||
|
|
@ -24,12 +24,6 @@ long_name := $(DESIGN_PACKAGE).$(DESIGN).$(TARGET_CONFIG)
|
|||
FIRRTL_FILE := $(GENERATED_DIR)/$(long_name).fir
|
||||
ANNO_FILE := $(GENERATED_DIR)/$(long_name).anno.json
|
||||
|
||||
ifdef FIRESIM_STANDALONE
|
||||
firesim_sbt_project := firesim
|
||||
else
|
||||
firesim_sbt_project := {file:${firesim_base_dir}/}firesim
|
||||
endif
|
||||
|
||||
chisel_src_dirs = \
|
||||
$(addprefix $(firesim_base_dir)/,. midas midas/targetutils firesim-lib) \
|
||||
$(addprefix $(chipyard_dir)/generators/, rocket-chip/src, rocket-chip/api-config-chipsalliance)
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@ long_name := $(DESIGN_PACKAGE).$(DESIGN).$(TARGET_CONFIG)
|
|||
FIRRTL_FILE := $(GENERATED_DIR)/$(long_name).fir
|
||||
ANNO_FILE := $(GENERATED_DIR)/$(long_name).anno.json
|
||||
|
||||
firesim_sbt_project := {file:$(firesim_base_dir)/}firesim
|
||||
chisel_src_dirs = \
|
||||
$(addprefix $(firesim_base_dir)/,. midas midas/targetutils firesim-lib) \
|
||||
$(addprefix $(chipyard_dir)/generators/, rocket-chip/src, rocket-chip/api-config-chipsalliance)
|
||||
|
|
|
|||
|
|
@ -30,7 +30,6 @@ FIRRTL_FILE := $(GENERATED_DIR)/$(long_name).fir
|
|||
ANNO_FILE := $(GENERATED_DIR)/$(long_name).anno.json
|
||||
|
||||
ifdef FIRESIM_STANDALONE
|
||||
firesim_sbt_project := {file:$(firesim_base_dir)/}firesim
|
||||
target_sbt_project := {file:${chipyard_dir}}firechip
|
||||
|
||||
lookup_scala_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "[!.]*.scala" -print 2> /dev/null)
|
||||
|
|
@ -38,7 +37,6 @@ ifdef FIRESIM_STANDALONE
|
|||
SCALA_SOURCES = $(call lookup_scala_srcs,$(SOURCE_DIRS))
|
||||
else
|
||||
target_sbt_project := firechip
|
||||
firesim_sbt_project := firechip
|
||||
endif
|
||||
|
||||
$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(FIRRTL_JAR) $(SCALA_BUILDTOOL_DEPS)
|
||||
|
|
@ -251,6 +249,8 @@ $(OUTPUT_DIR)/%.vpd: $(OUTPUT_DIR)/% $(EMUL)-debug
|
|||
./$(notdir $($(EMUL)_debug)) $< +waveform=$@ $($*_ARGS) $($(EMUL)_args) $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) \
|
||||
$(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
|
||||
|
||||
.PRECIOUS: $(OUTPUT_DIR)/%.vpd $(OUTPUT_DIR)/%.out $(OUTPUT_DIR)/%.run
|
||||
|
||||
# TraceGen rules
|
||||
|
||||
AXE_DIR=$(chipyard_dir)/tools/axe/src
|
||||
|
|
|
|||
|
|
@ -24,12 +24,6 @@ long_name := $(DESIGN_PACKAGE).$(DESIGN).$(TARGET_CONFIG)
|
|||
FIRRTL_FILE := $(GENERATED_DIR)/$(long_name).fir
|
||||
ANNO_FILE := $(GENERATED_DIR)/$(long_name).anno.json
|
||||
|
||||
ifdef FIRESIM_STANDALONE
|
||||
firesim_sbt_project := firesim
|
||||
else
|
||||
firesim_sbt_project := {file:${firesim_base_dir}/}firesim
|
||||
endif
|
||||
|
||||
chisel_src_dirs = \
|
||||
$(addprefix $(firesim_base_dir)/,. midas midas/targetutils firesim-lib) \
|
||||
$(addprefix $(chipyard_dir)/generators/, rocket-chip/src, rocket-chip/api-config-chipsalliance)
|
||||
|
|
|
|||
|
|
@ -1,368 +0,0 @@
|
|||
# See LICENSE for license details.
|
||||
|
||||
# FireSim Target Agnostic Make Fragment
|
||||
#
|
||||
# Defines make targets for:
|
||||
# - invoking Golden Gate (phony: verilog / compile)
|
||||
# - building a simulation driver (phony: f1)
|
||||
# - populating an FPGA build directory (phony: replace-rtl)
|
||||
# - generating new runtime configurations (phony: conf)
|
||||
# - compiling meta-simulators (phony: verilator, vcs, verilator-debug, vcs-debug)
|
||||
#
|
||||
|
||||
# The prefix used for all Golden Gate-generated files
|
||||
BASE_FILE_NAME ?=
|
||||
|
||||
# The directory into which generated verilog and headers will be dumped
|
||||
# RTL simulations will also be built here
|
||||
GENERATED_DIR ?=
|
||||
# Results from RTL simulations live here
|
||||
OUTPUT_DIR ?=
|
||||
# Root name for generated binaries
|
||||
DESIGN ?=
|
||||
|
||||
# The target's FIRRTL and associated anotations; inputs to Golden Gate
|
||||
FIRRTL_FILE ?=
|
||||
ANNO_FILE ?=
|
||||
|
||||
# The host config package and class string
|
||||
PLATFORM_CONFIG_PACKAGE ?= firesim.midasexamples
|
||||
PLATFORM_CONFIG ?= DefaultF1Config
|
||||
|
||||
# The name of the generated runtime configuration file
|
||||
CONF_NAME ?= $(BASE_FILE_NAME).runtime.conf
|
||||
|
||||
# The host platform type, currently only f1 is supported
|
||||
PLATFORM ?=
|
||||
|
||||
# Driver source files
|
||||
DRIVER_CC ?=
|
||||
DRIVER_H ?=
|
||||
|
||||
# Target-specific CXX and LD flags for compiling the driver and meta-simulators
|
||||
# These should be platform independent should be governed by the target-specific makefrag
|
||||
TARGET_CXX_FLAGS ?=
|
||||
TARGET_LD_FLAGS ?=
|
||||
|
||||
# END MAKEFRAG INTERFACE
|
||||
|
||||
# Defined for each platform
|
||||
platforms_dir := $(abspath $(firesim_base_dir)/../platforms)
|
||||
|
||||
simif_dir = $(firesim_base_dir)/midas/src/main/cc
|
||||
midas_h = $(shell find $(simif_dir) -name "*.h")
|
||||
midas_cc = $(shell find $(simif_dir) -name "*.cc")
|
||||
|
||||
common_cxx_flags := $(TARGET_CXX_FLAGS) -Wno-unused-variable
|
||||
common_ld_flags := $(TARGET_LD_FLAGS) -lrt
|
||||
|
||||
# Simulation memory map emitted by the MIDAS compiler
|
||||
header := $(GENERATED_DIR)/$(BASE_FILE_NAME).const.h
|
||||
# The midas-generated simulator RTL which will be baked into the FPGA shell project
|
||||
simulator_verilog := $(GENERATED_DIR)/$(BASE_FILE_NAME).sv
|
||||
|
||||
####################################
|
||||
# Golden Gate Invocation #
|
||||
####################################
|
||||
firesim_root_sbt_project := {file:$(firesim_base_dir)}firesim
|
||||
# Pre-simulation-mapping annotations which includes all Bridge Annotations
|
||||
# extracted used to generate new runtime configurations.
|
||||
fame_annos := $(GENERATED_DIR)/post-bridge-extraction.json
|
||||
|
||||
.PHONY: verilog compile
|
||||
verilog: $(simulator_verilog)
|
||||
compile: $(simulator_verilog)
|
||||
|
||||
# empty recipe to help make understand multiple targets come from single recipe invocation
|
||||
# without using the new (4.3) '&:' grouped targets see https://stackoverflow.com/a/41710495
|
||||
.SECONDARY: $(simulator_verilog).intermediate
|
||||
$(simulator_verilog) $(header) $(fame_annos): $(simulator_verilog).intermediate ;
|
||||
|
||||
# Disable FIRRTL 1.4 deduplication because it creates multiple failures
|
||||
# Run the 1.3 version instead (checked-in). If dedup must be completely disabled,
|
||||
# pass --no-legacy-dedup as well
|
||||
$(simulator_verilog).intermediate: $(FIRRTL_FILE) $(ANNO_FILE) $(SCALA_BUILDTOOL_DEPS)
|
||||
$(call run_scala_main,$(firesim_sbt_project),midas.stage.GoldenGateMain,\
|
||||
-i $(FIRRTL_FILE) \
|
||||
-td $(GENERATED_DIR) \
|
||||
-faf $(ANNO_FILE) \
|
||||
-ggcp $(PLATFORM_CONFIG_PACKAGE) \
|
||||
-ggcs $(PLATFORM_CONFIG) \
|
||||
--output-filename-base $(BASE_FILE_NAME) \
|
||||
--no-dedup \
|
||||
)
|
||||
grep -sh ^ $(GENERATED_DIR)/firrtl_black_box_resource_files.f | \
|
||||
xargs cat >> $(simulator_verilog) # Append blackboxes to FPGA wrapper, if any
|
||||
|
||||
####################################
|
||||
# Runtime-Configuration Generation #
|
||||
####################################
|
||||
|
||||
# This reads in the annotations from a generated target, elaborates a
|
||||
# FASEDTimingModel if a BridgeAnnoation for one exists, and asks for user input
|
||||
# to generate a runtime configuration that is compatible with the generated
|
||||
# hardware (BridgeModule). Useful for modelling a memory system that differs from the default.
|
||||
.PHONY: conf
|
||||
conf: $(fame_annos)
|
||||
mkdir -p $(GENERATED_DIR)
|
||||
cd $(base_dir) && $(SBT) "project $(firesim_sbt_project)" "runMain midas.stage.RuntimeConfigGeneratorMain \
|
||||
-td $(GENERATED_DIR) \
|
||||
-faf $(fame_annos) \
|
||||
-ggcp $(PLATFORM_CONFIG_PACKAGE) \
|
||||
-ggcs $(PLATFORM_CONFIG) \
|
||||
-ggrc $(CONF_NAME)"
|
||||
|
||||
####################################
|
||||
# Verilator MIDAS-Level Simulators #
|
||||
####################################
|
||||
|
||||
VERILATOR_CXXOPTS ?= -O0
|
||||
VERILATOR_MAKEFLAGS ?= -j8 VM_PARALLEL_BUILDS=1
|
||||
|
||||
verilator = $(GENERATED_DIR)/V$(DESIGN)
|
||||
verilator_debug = $(GENERATED_DIR)/V$(DESIGN)-debug
|
||||
|
||||
$(verilator) $(verilator_debug): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) $(VERILATOR_CXXOPTS) -D RTLSIM
|
||||
$(verilator) $(verilator_debug): export LDFLAGS := $(LDFLAGS) $(common_ld_flags) -Wl,-rpath='$$$$ORIGIN'
|
||||
|
||||
$(verilator): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h) $(simulator_verilog)
|
||||
$(MAKE) $(VERILATOR_MAKEFLAGS) -C $(simif_dir) verilator PLATFORM=$(PLATFORM) DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
|
||||
GEN_DIR=$(GENERATED_DIR) DRIVER="$(DRIVER_CC)" TOP_DIR=$(chipyard_dir) VERILATOR_FLAGS="$(EXTRA_VERILATOR_FLAGS)"
|
||||
|
||||
$(verilator_debug): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h) $(simulator_verilog)
|
||||
$(MAKE) $(VERILATOR_MAKEFLAGS) -C $(simif_dir) verilator-debug PLATFORM=$(PLATFORM) DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
|
||||
GEN_DIR=$(GENERATED_DIR) DRIVER="$(DRIVER_CC)" TOP_DIR=$(chipyard_dir) VERILATOR_FLAGS="$(EXTRA_VERILATOR_FLAGS)"
|
||||
|
||||
.PHONY: verilator verilator-debug
|
||||
verilator: $(verilator)
|
||||
verilator-debug: $(verilator_debug)
|
||||
|
||||
##############################
|
||||
# VCS MIDAS-Level Simulators #
|
||||
##############################
|
||||
|
||||
VCS_CXXOPTS ?= -O2
|
||||
|
||||
vcs = $(GENERATED_DIR)/$(DESIGN)
|
||||
vcs_debug = $(GENERATED_DIR)/$(DESIGN)-debug
|
||||
|
||||
$(vcs) $(vcs_debug): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) $(VCS_CXXOPTS) -I$(VCS_HOME)/include -D RTLSIM
|
||||
# VCS can mangle the ordering of libraries and object files at link time such
|
||||
# that some valid dependencies are pruned when --as-needed is set.
|
||||
# Conservatively set --no-as-needed in case --as-needed is defined in LDFLAGS.
|
||||
$(vcs) $(vcs_debug): export LDFLAGS := $(LDFLAGS) -Wl,--no-as-needed $(common_ld_flags) -Wl,-rpath='$$$$ORIGIN'
|
||||
|
||||
$(vcs): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h) $(simulator_verilog)
|
||||
$(MAKE) -C $(simif_dir) vcs PLATFORM=$(PLATFORM) DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
|
||||
GEN_DIR=$(GENERATED_DIR) DRIVER="$(DRIVER_CC)" TOP_DIR=$(chipyard_dir)
|
||||
|
||||
$(vcs_debug): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h) $(simulator_verilog)
|
||||
$(MAKE) -C $(simif_dir) vcs-debug PLATFORM=$(PLATFORM) DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
|
||||
GEN_DIR=$(GENERATED_DIR) DRIVER="$(DRIVER_CC)" TOP_DIR=$(chipyard_dir)
|
||||
|
||||
.PHONY: vcs vcs-debug
|
||||
vcs: $(vcs)
|
||||
vcs-debug: $(vcs_debug)
|
||||
|
||||
############################
|
||||
# Master Simulation Driver #
|
||||
############################
|
||||
DRIVER_CXXOPTS ?= -O2
|
||||
|
||||
$(PLATFORM) = $(OUTPUT_DIR)/$(DESIGN)-$(PLATFORM)
|
||||
$(PLATFORM): $($(PLATFORM))
|
||||
|
||||
.PHONY: driver
|
||||
driver: $(PLATFORM)
|
||||
|
||||
$(f1): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) $(DRIVER_CXXOPTS) \
|
||||
-I$(platforms_dir)/f1/aws-fpga/sdk/userspace/include
|
||||
# We will copy shared libs into same directory as driver on runhost, so add $ORIGIN to rpath
|
||||
$(f1): export LDFLAGS := $(LDFLAGS) $(common_ld_flags) -Wl,-rpath='$$$$ORIGIN' -L /usr/local/lib64 -lfpga_mgmt
|
||||
|
||||
# Compile Driver
|
||||
$(f1): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h)
|
||||
mkdir -p $(OUTPUT_DIR)/build
|
||||
cp $(header) $(OUTPUT_DIR)/build/
|
||||
$(MAKE) -C $(simif_dir) f1 PLATFORM=f1 DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
|
||||
GEN_DIR=$(OUTPUT_DIR)/build OUT_DIR=$(OUTPUT_DIR) DRIVER="$(DRIVER_CC)" \
|
||||
TOP_DIR=$(chipyard_dir)
|
||||
|
||||
$(vitis): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) $(DRIVER_CXXOPTS) \
|
||||
-idirafter ${CONDA_PREFIX}/include -idirafter /usr/include -idirafter $(XILINX_XRT)/include
|
||||
$(vitis): export LDFLAGS := $(LDFLAGS) $(common_ld_flags) -Wl,-rpath='$$$$ORIGIN' \
|
||||
-L${CONDA_PREFIX}/lib -Wl,-rpath-link=/usr/lib/x86_64-linux-gnu -L$(XILINX_XRT)/lib -luuid -lxrt_coreutil
|
||||
|
||||
|
||||
# Compile Driver
|
||||
$(vitis): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h)
|
||||
mkdir -p $(OUTPUT_DIR)/build
|
||||
cp $(header) $(OUTPUT_DIR)/build/
|
||||
$(MAKE) -C $(simif_dir) vitis PLATFORM=vitis DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
|
||||
GEN_DIR=$(OUTPUT_DIR)/build OUT_DIR=$(OUTPUT_DIR) DRIVER="$(DRIVER_CC)" \
|
||||
TOP_DIR=$(chipyard_dir)
|
||||
|
||||
#############################
|
||||
# FPGA Build Initialization #
|
||||
#############################
|
||||
ifeq ($(PLATFORM), vitis)
|
||||
board_dir := $(platforms_dir)/vitis
|
||||
else
|
||||
board_dir := $(platforms_dir)/f1/aws-fpga/hdk/cl/developer_designs
|
||||
endif
|
||||
|
||||
fpga_work_dir := $(board_dir)/cl_$(name_tuple)
|
||||
fpga_build_dir := $(fpga_work_dir)/build
|
||||
verif_dir := $(fpga_work_dir)/verif
|
||||
repo_state := $(fpga_work_dir)/design/repo_state
|
||||
fpga_driver_dir:= $(fpga_work_dir)/driver
|
||||
|
||||
# Enumerates the subset of generated files that must be copied over for FPGA compilation
|
||||
fpga_delivery_files = $(addprefix $(fpga_work_dir)/design/$(BASE_FILE_NAME), \
|
||||
.sv .defines.vh \
|
||||
.synthesis.xdc .implementation.xdc)
|
||||
|
||||
# Files used to run FPGA-level metasimulation
|
||||
fpga_sim_delivery_files = $(addprefix $(fpga_driver_dir)/$(BASE_FILE_NAME), .runtime.conf) \
|
||||
$(fpga_driver_dir)/$(DESIGN)-$(PLATFORM)
|
||||
|
||||
$(fpga_work_dir)/stamp: $(shell find $(board_dir)/cl_firesim -name '*')
|
||||
mkdir -p $(driver_dir) #Could just set up in the shell project
|
||||
cp -rf $(board_dir)/cl_firesim -T $(fpga_work_dir)
|
||||
touch $@
|
||||
|
||||
$(repo_state): $(simulator_verilog) $(fpga_work_dir)/stamp
|
||||
$(firesim_base_dir)/../scripts/repo_state_summary.sh > $(repo_state)
|
||||
|
||||
$(fpga_work_dir)/design/$(BASE_FILE_NAME)%: $(simulator_verilog) $(fpga_work_dir)/stamp
|
||||
cp -f $(GENERATED_DIR)/*.ipgen.tcl $(@D) || true
|
||||
cp -f $(GENERATED_DIR)/$(@F) $@
|
||||
|
||||
$(fpga_driver_dir)/$(BASE_FILE_NAME)%: $(simulator_verilog) $(fpga_work_dir)/stamp
|
||||
mkdir -p $(@D)
|
||||
cp -f $(GENERATED_DIR)/$(@F) $@
|
||||
|
||||
$(fpga_driver_dir)/$(DESIGN)-$(PLATFORM): $($(PLATFORM))
|
||||
cp -f $< $@
|
||||
|
||||
# Goes as far as setting up the build directory without running the cad job
|
||||
# Used by the manager before passing a build to a remote machine
|
||||
replace-rtl: $(fpga_delivery_files) $(fpga_sim_delivery_files)
|
||||
|
||||
.PHONY: replace-rtl
|
||||
|
||||
$(firesim_base_dir)/scripts/checkpoints/$(target_sim_tuple): $(fpga_work_dir)/stamp
|
||||
mkdir -p $(@D)
|
||||
ln -sf $(fpga_build_dir)/checkpoints/to_aws $@
|
||||
|
||||
# Runs a local fpga-bitstream build. Strongly consider using the manager instead.
|
||||
fpga: export CL_DIR := $(fpga_work_dir)
|
||||
fpga: $(fpga_delivery_files) $(base_dir)/scripts/checkpoints/$(target_sim_tuple)
|
||||
cd $(fpga_build_dir)/scripts && ./aws_build_dcp_from_cl.sh -notify
|
||||
|
||||
|
||||
#############################
|
||||
# FPGA-level RTL Simulation #
|
||||
#############################
|
||||
|
||||
# Run XSIM DUT
|
||||
.PHONY: xsim-dut
|
||||
xsim-dut: replace-rtl $(fpga_work_dir)/stamp
|
||||
cd $(verif_dir)/scripts && $(MAKE) C_TEST=test_firesim
|
||||
|
||||
# Compile XSIM Driver #
|
||||
xsim = $(GENERATED_DIR)/$(DESIGN)-$(PLATFORM)
|
||||
|
||||
$(xsim): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) -D SIMULATION_XSIM -D NO_MAIN
|
||||
$(xsim): export LDFLAGS := $(LDFLAGS) $(common_ld_flags)
|
||||
$(xsim): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h)
|
||||
$(MAKE) -C $(simif_dir) f1 PLATFORM=f1 DRIVER_NAME=$(DESIGN) GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
|
||||
GEN_DIR=$(GENERATED_DIR) OUT_DIR=$(GENERATED_DIR) DRIVER="$(DRIVER_CC)" \
|
||||
TOP_DIR=$(chipyard_dir)
|
||||
|
||||
.PHONY: xsim
|
||||
xsim: $(xsim)
|
||||
|
||||
#########################
|
||||
# MIDAS Unit Tests #
|
||||
#########################
|
||||
UNITTEST_CONFIG ?= AllUnitTests
|
||||
|
||||
rocketchip_dir := $(chipyard_dir)/generators/rocket-chip
|
||||
unittest_generated_dir := $(base_dir)/generated-src/unittests/$(UNITTEST_CONFIG)
|
||||
unittest_args = \
|
||||
BASE_DIR=$(base_dir) \
|
||||
EMUL=$(EMUL) \
|
||||
ROCKETCHIP_DIR=$(rocketchip_dir) \
|
||||
GEN_DIR=$(unittest_generated_dir) \
|
||||
SBT="$(SBT)" \
|
||||
SBT_PROJECT=$(firesim_root_sbt_project) \
|
||||
CONFIG=$(UNITTEST_CONFIG) \
|
||||
TOP_DIR=$(chipyard_dir)
|
||||
|
||||
.PHONY:compile-midas-unittests
|
||||
compile-midas-unittests: $(chisel_srcs)
|
||||
$(MAKE) -f $(simif_dir)/unittest/Makefrag $(unittest_args)
|
||||
|
||||
.PHONY:run-midas-unittests
|
||||
run-midas-unittests: $(chisel_srcs)
|
||||
$(MAKE) -f $(simif_dir)/unittest/Makefrag $@ $(unittest_args)
|
||||
|
||||
.PHONY:run-midas-unittests-debug
|
||||
run-midas-unittests-debug: $(chisel_srcs)
|
||||
$(MAKE) -f $(simif_dir)/unittest/Makefrag $@ $(unittest_args)
|
||||
|
||||
#########################
|
||||
# ScalaDoc #
|
||||
#########################
|
||||
scaladoc:
|
||||
cd $(base_dir) && $(SBT) "project {file:$(firesim_base_dir)}firesim" "unidoc"
|
||||
|
||||
.PHONY: scaladoc
|
||||
|
||||
#########################
|
||||
# Scalafmt #
|
||||
#########################
|
||||
# Checks that all scala main sources under firesim SBT subprojects are formatted.
|
||||
scalafmtCheckAll:
|
||||
cd $(base_dir) && $(SBT) ";project {file:$(firesim_base_dir)}firesim; \
|
||||
firesim / scalafmtCheckAll; \
|
||||
firesimLib / scalafmtCheckAll; \
|
||||
midas / scalafmtCheckAll ; \
|
||||
targetutils / scalafmtCheckAll ;"
|
||||
|
||||
# Runs the code reformatter in all firesim SBT subprojects
|
||||
scalafmtAll:
|
||||
cd $(base_dir) && $(SBT) ";project {file:$(firesim_base_dir)}firesim; \
|
||||
firesim / scalafmtAll; \
|
||||
firesimLib / scalafmtAll; \
|
||||
midas / scalafmtAll ; \
|
||||
targetutils / scalafmtAll ;"
|
||||
|
||||
.PHONY: scalafmtCheckAll scalafmtAll
|
||||
#########################
|
||||
# Cleaning Recipes #
|
||||
#########################
|
||||
cleanfpga:
|
||||
rm -rf $(fpga_work_dir)
|
||||
|
||||
mostlyclean:
|
||||
rm -rf $(verilator) $(verilator_debug) $(vcs) $(vcs_debug) $($(PLATFORM)) $(OUTPUT_DIR)
|
||||
|
||||
clean:
|
||||
rm -rf $(GENERATED_DIR) $(OUTPUT_DIR)
|
||||
|
||||
veryclean:
|
||||
rm -rf generated-src output
|
||||
|
||||
tags: $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h)
|
||||
ctags -R --exclude=@.ctagsignore .
|
||||
|
||||
.PHONY: $(PLATFORM)-driver fpga
|
||||
.PHONY: mostlyclean clean
|
||||
|
||||
.PRECIOUS: $(OUTPUT_DIR)/%.vpd $(OUTPUT_DIR)/%.out $(OUTPUT_DIR)/%.run
|
||||
|
||||
# Remove all implicit suffix rules; This improves make performance substantially as it no longer
|
||||
# attempts to resolve implicit rules on 1000+ scala files.
|
||||
.SUFFIXES:
|
||||
Loading…
Reference in New Issue