2aea76181a
Merge pull request #38 from ucb-bar/chisel3-switch
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Switch to chisel3
2017-02-08 10:09:01 -08:00
4a1d0d98ed
switch to chisel3
2017-02-07 18:06:05 -08:00
8d5981cdab
Update README to uniformly suggest vivado 2016.2
2017-01-10 16:19:12 -08:00
ac39be1c1f
get README.md up to date
2016-11-01 13:35:25 -07:00
eb96e9db7f
replace init-rocket-submodule with init-submodules rule in Makefrag
2016-11-01 13:34:54 -07:00
9a0b82d0c4
update FPGA images
2016-10-28 13:52:38 -07:00
3ed82263c4
use TestDriver.v in rocket-chip not in testchipip
2016-10-24 17:19:32 -07:00
03e919a86a
NoDebug trait moved to testchipip
2016-10-24 17:19:24 -07:00
947e3bae46
move TestDriver.v into testchipip
2016-10-24 17:19:15 -07:00
33b1e90efc
make sure to use the correct kind of include for Makefrag.pkgs
2016-10-24 17:19:08 -07:00
1ef84b9171
make sure simulation directory has src/verilog folder
2016-10-17 16:26:21 -07:00
31f0bd2422
make sure library stamps have correct dependencies
2016-10-11 11:42:46 -07:00
f6978c40e0
make submodule building more extensible
2016-10-10 16:42:09 -07:00
42959c7514
get rid of generated verilog files
2016-10-07 16:57:01 -07:00
e2cf7799cc
bump rocket-chip submodule pointer to get riscv-fesvr change
2016-10-07 16:50:19 -07:00
07c02e7a0f
SAI renamed to TSI
2016-10-07 15:20:38 -07:00
d1f80398fb
move simulation serial into testchipip
2016-10-07 14:59:10 -07:00
685731faf1
make sure Zybo configuration has virtual memory
2016-10-07 14:16:20 -07:00
640e64cb5a
add ability to reset target through AXI
2016-10-06 21:20:46 -07:00
73f1a41a68
fix issues with NastiFIFO
2016-10-06 17:45:50 -07:00
3d4a544d8d
make integration test use single-beat bursts
2016-10-06 14:46:08 -07:00
4d707d3ab0
fix integration test and make it test NastiFIFO
2016-10-05 11:12:24 -07:00
2f665ca9cf
fix up NastiFIFO to take multi-beat reads
2016-10-05 11:12:03 -07:00
79697316de
replace dtm driver with sai driver
2016-10-05 09:26:49 -07:00
0e8e494570
fixups to serial adapter
2016-10-04 18:34:41 -07:00
cfc9f33973
get rid of top-level riscv-fesvr submodule; use one in riscv-tools
2016-10-04 17:59:33 -07:00
11a6c0e7e2
update to latest rocketchip master
2016-10-04 16:51:47 -07:00
5cddc881ad
move SerialAdapter code to testchipip
2016-10-04 14:52:49 -07:00
75b4ea3775
add our own version of the bootrom
2016-10-04 13:23:50 -07:00
85a98e6f05
actually implement SimSerial
2016-10-04 13:19:11 -07:00
b91b06e8de
get rid of reset in Adapter
2016-10-04 13:18:47 -07:00
d392485525
allow host to read how much data/space is available in FIFOs
2016-10-03 17:03:38 -07:00
8a18edde38
get rid of interrupts and slave device in adapter
2016-10-03 17:02:45 -07:00
3f3e755d6a
fix up makefiles
2016-10-03 16:59:41 -07:00
bbc47cae6e
add riscv-fesvr submodule
2016-10-03 09:20:01 -07:00
f3f3a44386
rename ZynqAdapter to SerialAdapter
2016-09-29 13:10:53 -07:00
bf036fb956
start implementing alternate adapter interface
2016-09-29 12:44:47 -07:00
98669e298f
update to post- cake pattern refactor rocketchip
2016-09-22 12:04:51 -07:00
86d2cf1de7
Bump zybo images to include functional bbl instance
2016-09-09 10:35:30 -07:00
6c06d97cb1
Conform to new rocketchip generator. Fix adapter concat bugs
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This brings fpga-zynq up to sync with Henry's changes to rocket-chip
generation utilities. It also fixes a silly bug that assumed constant
field orderings when toBits-ing an aggregate.
2016-09-08 16:48:59 -07:00
425c111d11
Merge pull request #19 from bkoppelmann/vivado-readme
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Fix README to show the fact, that we now require Vivado 2016.2
2016-09-06 10:14:51 -07:00
0e5105930c
Fix README to show the fact, that we now require Vivado 2016.2
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Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2016-09-06 15:54:52 +02:00
b6bed1d20a
Actually fix local configuration lookup
2016-08-24 14:40:46 -07:00
3246c61b17
Fix local configuration lookup
2016-08-24 14:34:13 -07:00
e37714dc80
Bump zybo images
2016-08-24 10:32:15 -07:00
dc3a871e65
Bump zedboard, zc706 image submodules
2016-08-23 14:13:33 -07:00
66093b4a32
Upgrade projects to version 2016.2
2016-08-18 12:43:19 -07:00
74ed9ea984
Fix copy of generated verilog to project
2016-08-17 16:45:30 -07:00
33dcf3efa7
Makefile bug fixes, generator config lookup enhancement
2016-08-17 14:10:53 -07:00
26b368e105
Merge pull request #15 from ucb-bar/dtm_bring_up
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Rocket as a library & NASTI <-> DTM support
2016-08-13 09:30:57 -07:00
David Biancolin