add ability to reset target through AXI
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73f1a41a68
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@ -6,10 +6,11 @@
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#include <assert.h>
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#define SAI_BASE_PADDR 0x43C00000L
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#define SAI_OUT_FIFO_DATA 0x0
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#define SAI_OUT_FIFO_COUNT 0x4
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#define SAI_IN_FIFO_DATA 0x8
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#define SAI_IN_FIFO_COUNT 0xC
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#define SAI_OUT_FIFO_DATA 0x00
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#define SAI_OUT_FIFO_COUNT 0x04
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#define SAI_IN_FIFO_DATA 0x08
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#define SAI_IN_FIFO_COUNT 0x0C
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#define SAI_SYS_RESET 0x10
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zynq_sai_driver_t::zynq_sai_driver_t()
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{
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@ -17,6 +18,10 @@ zynq_sai_driver_t::zynq_sai_driver_t()
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assert(fd != -1);
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dev = (uint8_t *) mmap(0, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, SAI_BASE_PADDR);
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assert(dev != MAP_FAILED);
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// reset the target
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write(SAI_SYS_RESET, 1);
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write(SAI_SYS_RESET, 0);
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}
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@ -13,6 +13,7 @@ class WithZynqAdapter extends Config(
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(pname, site, here) => pname match {
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case SerialInterfaceWidth => 32
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case SerialFIFODepth => 16
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case ResetCycles => 10
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case BuildSerialDriver =>
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(p: Parameters) => Module(new SimSerialWrapper(p(SerialInterfaceWidth)))
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case _ => throw new CDEMatchError
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@ -143,12 +143,41 @@ class IntegrationTestDriver(implicit p: Parameters) extends NastiModule()(p) {
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"Integration test data mismatch")
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}
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class IntegrationTestReset(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val nasti = new NastiIO
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}
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val (s_idle :: s_write_addr :: s_write_data :: s_done :: Nil) = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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when (state === s_idle) { state := s_write_addr }
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when (io.nasti.aw.fire()) { state := s_write_data }
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when (io.nasti.w.fire()) { state := s_done }
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io.nasti.aw.valid := state === s_write_addr
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0x43C00010L),
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size = UInt(2))
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io.nasti.w.valid := state === s_write_data
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io.nasti.w.bits := NastiWriteDataChannel(data = UInt(0))
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io.nasti.b.ready := (state === s_done)
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io.nasti.ar.valid := Bool(false)
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io.nasti.r.ready := Bool(false)
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}
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class IntegrationTestSerial(implicit p: Parameters) extends SerialDriver(p(SerialInterfaceWidth)) {
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val testParams = AdapterParams(p)
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val fifo = Module(new NastiFIFO()(testParams))
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val slave = Module(new ZynqAXISlave(2)(testParams))
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val driver = Module(new IntegrationTestDriver()(testParams))
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val resetter = Module(new IntegrationTestReset()(testParams))
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io.exit := driver.io.exit
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fifo.io.nasti <> driver.io.nasti
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fifo.io.serial <> io.serial
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slave.io.nasti(0) <> driver.io.nasti
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slave.io.nasti(1) <> resetter.io.nasti
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slave.io.serial <> io.serial
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driver.reset := slave.io.sys_reset
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}
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@ -8,12 +8,14 @@ import junctions.NastiConstants._
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import cde.{Parameters, Field}
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import rocketchip._
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import uncore.devices.{DebugBusIO}
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import uncore.tilelink.ClientUncachedTileLinkIOCrossbar
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import testchipip._
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import coreplex.BaseCoreplexBundle
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import java.io.File
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case object SerialFIFODepth extends Field[Int]
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case object ResetCycles extends Field[Int]
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class Top(implicit val p: Parameters) extends Module {
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val io = new Bundle {
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@ -22,7 +24,7 @@ class Top(implicit val p: Parameters) extends Module {
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}
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val target = LazyModule(new FPGAZynqTop(p)).module
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val fifo = Module(new NastiFIFO()(AdapterParams(p)))
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val slave = Module(new ZynqAXISlave(1)(AdapterParams(p)))
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require(target.io.mem_axi.size == 1)
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require(target.io.mem_ahb.isEmpty)
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@ -31,8 +33,94 @@ class Top(implicit val p: Parameters) extends Module {
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require(target.io.mem_rst.isEmpty)
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io.mem_axi <> target.io.mem_axi.head
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fifo.io.nasti <> io.ps_axi_slave
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fifo.io.serial <> target.io.serial
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slave.io.nasti.head <> io.ps_axi_slave
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slave.io.serial <> target.io.serial
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target.reset := slave.io.sys_reset
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}
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class ZynqAXISlave(nPorts: Int)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val nasti = Vec(nPorts, new NastiIO()).flip
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val sys_reset = Bool(OUTPUT)
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val serial = new SerialIO(p(SerialInterfaceWidth)).flip
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}
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def routeSel(addr: UInt): UInt = {
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// 0x00 - 0x0F go to FIFO
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// 0x10 goes to Reset generator
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UIntToOH(addr(4))
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}
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val xbar = Module(new NastiCrossbar(nPorts, 2, routeSel _))
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val fifo = Module(new NastiFIFO)
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val resetter = Module(new ResetController)
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xbar.io.masters <> io.nasti
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fifo.io.nasti <> xbar.io.slaves(0)
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fifo.io.serial <> io.serial
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resetter.io.nasti <> xbar.io.slaves(1)
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io.sys_reset := resetter.io.sys_reset
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}
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class ResetController(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = new NastiIO().flip
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val sys_reset = Bool(OUTPUT)
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}
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val reg_reset = Reg(init = Bool(true))
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val readId = Reg(UInt(width = nastiXIdBits))
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val r_addr :: r_data :: Nil = Enum(Bits(), 2)
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val r_state = Reg(init = r_addr)
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io.nasti.ar.ready := r_state === r_addr
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io.nasti.r.valid := r_state === r_data
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io.nasti.r.bits := NastiReadDataChannel(
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id = readId,
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data = reg_reset)
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when (io.nasti.ar.fire()) {
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readId := io.nasti.ar.bits.id
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r_state := r_data
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}
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when (io.nasti.r.fire()) {
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r_state := r_addr
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}
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val writeId = Reg(UInt(width = nastiXIdBits))
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val w_addr :: w_data :: w_resp :: Nil = Enum(Bits(), 3)
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val w_state = Reg(init = w_addr)
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val timer = Reg(init = UInt(p(ResetCycles) - 1))
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// Make sure reset period lasts for a certain number of cycles
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when (timer =/= UInt(0)) { timer := timer - UInt(1) }
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when (io.nasti.aw.fire()) {
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writeId := io.nasti.aw.bits.id
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w_state := w_data
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}
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when (io.nasti.w.fire()) {
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timer := UInt(p(ResetCycles) - 1)
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reg_reset := io.nasti.w.bits.data(0)
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w_state := w_resp
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}
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when (io.nasti.b.fire()) {
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w_state := w_addr
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}
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io.nasti.aw.ready := w_state === w_addr
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io.nasti.w.ready := w_state === w_data
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io.nasti.b.valid := w_state === w_resp && timer === UInt(0)
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io.nasti.b.bits := NastiWriteResponseChannel(id = writeId)
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io.sys_reset := reg_reset
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}
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class NastiFIFO(implicit p: Parameters) extends NastiModule()(p) {
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