hustos
/
fpga-pynq
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

move TestDriver.v into testchipip

This commit is contained in:
Howard Mao 2016-10-21 14:13:39 -07:00
parent 33b1e90efc
commit 947e3bae46
3 changed files with 2 additions and 93 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

91
common/vsrc/TestDriver.v
View File

@ -1,91 +0,0 @@
// See LICENSE for license details.
`ifndef RESET_DELAY
`define RESET_DELAY 777.7
`endif
module TestDriver;
reg clock = 1'b0;
reg reset = 1'b1;
always #(`CLOCK_PERIOD/2.0) clock = ~clock;
initial #(`RESET_DELAY) reset = 0;
// Read input arguments and initialize
reg verbose = 1'b0;
wire printf_cond = verbose && !reset;
reg [63:0] max_cycles = 0;
reg [63:0] trace_count = 0;
reg [1023:0] vcdplusfile = 0;
reg [1023:0] vcdfile = 0;
initial
begin
$value$plusargs("max-cycles=%d", max_cycles);
verbose = $test$plusargs("verbose");
`ifdef DEBUG
if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
begin
$vcdplusfile(vcdplusfile);
$vcdpluson(0);
$vcdplusmemon(0);
end
if ($value$plusargs("vcdfile=%s", vcdfile))
begin
$dumpfile(vcdfile);
$dumpvars(0, testHarness);
$dumpon;
end
`define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
`else
`define VCDPLUSCLOSE
`endif
end
reg [255:0] reason = "";
reg failure = 1'b0;
wire success;
integer stderr = 32'h80000002;
always @(posedge clock)
begin
`ifdef GATE_LEVEL
if (verbose)
begin
$fdisplay(stderr, "C: %10d", trace_count);
end
`endif
trace_count = trace_count + 1;
if (!reset)
begin
if (max_cycles > 0 && trace_count > max_cycles)
begin
reason = " (timeout)";
failure = 1'b1;
end
if (failure)
begin
$fdisplay(stderr, "*** FAILED ***%s after %d simulation cycles", reason, trace_count);
`VCDPLUSCLOSE
$fatal;
end
if (success)
begin
if (verbose)
$fdisplay(stderr, "Completed after %d simulation cycles", trace_count);
`VCDPLUSCLOSE
$finish;
end
end
end
TestHarness testHarness(
.clock (clock),
.reset (reset),
.io_success (success)
);
endmodule

2
simulation/Makefile
View File

@ -12,7 +12,7 @@ include ../common/Makefrag
sim_vsrcs = \
src/verilog/$(TOP_MODULE).$(CONFIG).v \
$(common)/vsrc/TestDriver.v \
$(base_dir)/testchipip/vsrc/TestDriver.v \
$(base_dir)/testchipip/vsrc/SimSerial.v
sim_csrcs = \

2
testchipip

@ -1 +1 @@
Subproject commit fdd6612edc4ee63e1afb2b69cc429b5b80ce4474
Subproject commit 1302c62a32c89e54c9967f3007845827e4c6f7d0