allow host to read how much data/space is available in FIFOs
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parent
8a18edde38
commit
d392485525
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@ -57,10 +57,21 @@ class NastiFIFO(implicit p: Parameters) extends NastiModule()(p) {
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io.nasti.w.ready := inq.io.enq.ready && writing
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inq.io.enq.bits := io.nasti.w.bits.data
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io.nasti.r.valid := outq.io.deq.valid && reading
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outq.io.deq.ready := io.nasti.r.ready && reading
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val nRegisters = 3
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val addrLSB = log2Up(w / 8)
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val addrMSB = addrLSB + log2Up(nRegisters) - 1
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val araddr = io.nasti.ar.bits.addr(addrMSB, addrLSB)
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val awaddr = io.nasti.aw.bits.addr(addrMSB, addrLSB)
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val raddr = Reg(araddr)
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io.nasti.r.valid := reading && (raddr =/= UInt(0) || outq.io.deq.valid)
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outq.io.deq.ready := reading && (raddr =/= UInt(0) || io.nasti.r.ready)
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io.nasti.r.bits := NastiReadDataChannel(
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id = rid, data = outq.io.deq.bits)
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id = rid,
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data = MuxLookup(raddr, UInt(0), Seq(
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UInt(0) -> outq.io.deq.bits,
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UInt(1) -> outq.io.count, // available output FIFO data
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UInt(2) -> (UInt(depth) - inq.io.count)))) // free input FIFO space
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io.nasti.aw.ready := !writing && !responding
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io.nasti.ar.ready := !reading
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@ -79,6 +90,7 @@ class NastiFIFO(implicit p: Parameters) extends NastiModule()(p) {
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when (io.nasti.ar.fire()) {
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len := io.nasti.ar.bits.len
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rid := io.nasti.ar.bits.id
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raddr := araddr
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reading := Bool(true)
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}
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when (io.nasti.r.fire() && io.nasti.r.bits.last) { reading := Bool(false) }
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