hustos
/
fpga-pynq
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

make submodule building more extensible

This commit is contained in:
Howard Mao 2016-10-10 16:42:09 -07:00
parent 42959c7514
commit f6978c40e0
2 changed files with 11 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
common/Makefrag
View File

@ -2,11 +2,11 @@
JOBS = 16
ROCKET_DIR ?= $(base_dir)/rocket-chip
TESTCHIP_DIR ?= $(base_dir)/testchipip
TOP_MODULE_PROJECT ?= zynq
TOP_MODULE ?= Top
CFG_PROJECT ?= $(TOP_MODULE_PROJECT)
CONFIG ?= ZynqConfig
EXTRA_PACKAGES=testchipip
base_dir = $(abspath ..)
common = $(base_dir)/common
@ -16,7 +16,7 @@ SHELL := /bin/bash
bootrom_img = $(common)/bootrom/bootrom.img
rocketchip_stamp = $(common)/lib/rocketchip.stamp
testchipip_stamp = $(common)/lib/testchipip.stamp
extra_stamps = $(addprefix $(common)/lib/,$(addsuffix .stamp,$(EXTRA_PACKAGES)))
ifneq ($(BOARD_MODEL),)
insert_board = s/\# REPLACE FOR OFFICIAL BOARD NAME/set_property "board_part" "$(BOARD_MODEL)"/g
@ -71,13 +71,14 @@ $(rocketchip_stamp): $(call lookup_scala_srcs, $(ROCKET_DIR))
cp $(ROCKET_DIR)/target/pack/lib/* $(common)/lib
touch $(rocketchip_stamp)
$(testchipip_stamp): $(call lookup_scala_srcs, $(TESTCHIP_DIR)) $(rocketchip_stamp)
ln -sf $(common)/lib $(TESTCHIP_DIR)/lib
cd $(TESTCHIP_DIR) && $(SBT) package
cp $(TESTCHIP_DIR)/target/scala-2.11/*.jar $(common)/lib
touch $(testchipip_stamp)
$(common)/%.stamp: $(call lookup_scala_srcs, %) $(rocketchip_stamp)
rm -f $(base_dir)/$(patsubst %.stamp,%,$(notdir $@))/lib
ln -s $(common)/lib $(base_dir)/$(patsubst %.stamp,%,$(notdir $@))/lib
cd $(base_dir)/$(patsubst %.stamp,%,$(notdir $@)) && $(SBT) package
cp $(base_dir)/$(patsubst %.stamp,%,$(notdir $@))/target/scala-2.11/*.jar $(common)/lib
touch $@
$(common_build)/$(TOP_MODULE).$(CONFIG).fir: $(rocketchip_stamp) $(testchipip_stamp) $(bootrom_img) $(call lookup_scala_srcs,$(common))
$(common_build)/$(TOP_MODULE).$(CONFIG).fir: $(rocketchip_stamp) $(extra_stamps) $(bootrom_img) $(call lookup_scala_srcs,$(common))
mkdir -p $(@D)
cd $(common) && $(SBT) "run $(CHISEL_ARGS) $(TOP_MODULE_PROJECT) $(TOP_MODULE) $(CFG_PROJECT) $(CONFIG)"

4
simulation/Makefile
View File

@ -13,10 +13,10 @@ include ../common/Makefrag
sim_vsrcs = \
src/verilog/$(TOP_MODULE).$(CONFIG).v \
$(common)/vsrc/TestDriver.v \
$(TESTCHIP_DIR)/vsrc/SimSerial.v
$(base_dir)/testchipip/vsrc/SimSerial.v
sim_csrcs = \
$(TESTCHIP_DIR)/csrc/SimSerial.cc
$(base_dir)/testchipip/csrc/SimSerial.cc
VCS = vcs -full64