Libraries
Utils
State less utilities
State full utilities
Counter
Timeout
ResetCtrl
Special utilities
Stream
Specification
Semantics
Functions
Utils
StreamFifo
StreamFifoCC
StreamCCByTogggle
StreamWidthAdapter
StreamAribiter
StreamJoin
StyreamFork
StreamDispatcherSequencial
Flow
Specification
Functions
Code example
Fragment
Specification
Functions
State machine
Introduction
StateMachine
Entry point
Transitions
States
StateDelay
StateFsm
StateParallelFsm
Notes about the entry state
VexRiscv(RV32IM CPU)
Bus Slave Factory
Introduction
Functionality
Fiber Framework
Simple dummy example
Handle[T]
soon(handle)
BinarySystem
Specification
String to Int/Long/BigInt
Int/Long/BigInt to String
Int/Long/BigInt to Binary-List
Binary-List to Int/Long/bigInt
BigInt enricher
Regif
Automatic allocation
28 ACCess Types
Automatic documentation generation
Example
Interrupt Factory
Interrupt Design Spec
IP level interrupt Factory
SYS level interrupt merge
Spinal Factory
Example
Developers Area
Bus
AHB-Lite3
Configuration and instanciation
Variations
Apb3
Introduction
Configuration and instanciation
Functions and operators
Axi4
Introduction
Configuration and instanciation
Variations
Functions and operators
AvalonMM
Introduction
Configuration and instanciation
Com
UART
Introduction
Bus definition
UartCtral
USB device
Introduction
Architecture
Registers
Descriptors
Usage
USB OHCI
Introduction
Usage
IO
ReadableOpenDrain
ReadableOpenDrain
TriState
Introduction
TriState
TriStateArray
Graphics
Colors
RGB
VGA
VGA bus
VGA timing
VGA controller
EDA
QSysify
Introduction
Example
tags
Adding new interface support
QuartusFlow
Introduction
For a single rtl file
For an exising project
Misc
Plic Mapper
PlicMapper.apply
PlicMapping.sifive
PlicMapping.light
Introduction
Introduction