forked from opendacs/PyHCL
159 lines
2.3 KiB
Markdown
159 lines
2.3 KiB
Markdown
# Libraries
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## Utils
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### State less utilities
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### State full utilities
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#### Counter
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#### Timeout
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#### ResetCtrl
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### Special utilities
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## Stream
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### Specification
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### Semantics
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### Functions
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### Utils
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#### StreamFifo
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#### StreamFifoCC
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#### StreamCCByTogggle
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#### StreamWidthAdapter
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#### StreamAribiter
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#### StreamJoin
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#### StyreamFork
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#### StreamDispatcherSequencial
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## Flow
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### Specification
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### Functions
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### Code example
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## Fragment
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### Specification
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### Functions
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## State machine
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### Introduction
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### StateMachine
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#### Entry point
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#### Transitions
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### States
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#### StateDelay
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#### StateFsm
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#### StateParallelFsm
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#### Notes about the entry state
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## VexRiscv(RV32IM CPU)
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## Bus Slave Factory
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### Introduction
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### Functionality
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## Fiber Framework
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### Simple dummy example
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### Handle[T]
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#### soon(handle)
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## BinarySystem
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### Specification
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### String to Int/Long/BigInt
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### Int/Long/BigInt to String
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### Int/Long/BigInt to Binary-List
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### Binary-List to Int/Long/bigInt
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### BigInt enricher
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## Regif
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### Automatic allocation
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### 28 ACCess Types
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### Automatic documentation generation
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### Example
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### Interrupt Factory
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## Interrupt Design Spec
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### IP level interrupt Factory
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### SYS level interrupt merge
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### Spinal Factory
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### Example
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### Developers Area
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## Bus
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### AHB-Lite3
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#### Configuration and instanciation
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#### Variations
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### Apb3
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#### Introduction
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#### Configuration and instanciation
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#### Functions and operators
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### Axi4
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#### Introduction
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#### Configuration and instanciation
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#### Variations
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#### Functions and operators
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### AvalonMM
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#### Introduction
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#### Configuration and instanciation
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## Com
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### UART
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#### Introduction
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#### Bus definition
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#### UartCtral
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### USB device
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#### Introduction
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#### Architecture
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#### Registers
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#### Descriptors
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#### Usage
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### USB OHCI
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#### Introduction
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#### Usage
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## IO
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### ReadableOpenDrain
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#### ReadableOpenDrain
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### TriState
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#### Introduction
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#### TriState
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#### TriStateArray
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## Graphics
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### Colors
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#### RGB
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### VGA
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#### VGA bus
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#### VGA timing
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#### VGA controller
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## EDA
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### QSysify
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#### Introduction
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#### Example
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#### tags
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#### Adding new interface support
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### QuartusFlow
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#### Introduction
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#### For a single rtl file
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#### For an exising project
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## Misc
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### Plic Mapper
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#### PlicMapper.apply
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#### PlicMapping.sifive
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#### PlicMapping.light
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## Introduction
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### Introduction |