PyHCL/docs

Welcome to the PyHCL Documentation

Site purpose and structure

This site presents the PyHCL language and how to use it on concrete examples.

What is PyHCL

PyHCL is a hardware construct language like Chisel but more lightweight and more relaxed to use. As a novel hardware construction framework embedded in Python, PyHCL supports several useful features include object-oriented, functional programming, and dynamically typed objects.

The goal of PyHCL is providing a complete design and verification tool flow for heterogeneous computing systems flexibly using the same design methodology.

PyHCL is powered by FIRRTL, an intermediate representation for digital circuit design. With the FIRRTL compiler framework, PyHCL-generated circuits can be compiled to the widely-used HDL Verilog.

Similar Projects

• autofpga - C++, A utility for Composing FPGA designs from Peripherals
• BinPy - Python, An electronic simulation library
• blarney - Haskell, HCL
• bsc - Haskell, C++, BSV - Bluespec Compiler
• chisel - 2012-?, Scala, HCL
• Chips-2.0 - , , FPGA Design Suite based on C to Verilog design flow
• circt - 2020-?, C++/LLVM, compiler infrastructure
• circuitgraph - Tools for working with circuits as graphs in python
• concat - 2016-?, Haskell, Haskell to hardware
• DUH - JS, simple convertor between verilog/scala/ipxact
• DFiant 2019-?, Scala, dataflow based HDL
• edalize - 2018-?, Python, abstraction layer for eda tools
• garnet -2018-?, Python, Coarse-Grained Reconfigurable Architecture generator based on magma
• hammer - 2017-?, Python, Highly Agile Masks Made Effortlessly from RTL
• heterocl - 2017-?, C++, A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing
• hoodlum - 2016-?, Rust, HCL
• ILAng - modeling and verification platform for SoCs where Instruction-Level Abstraction (ILA) is used as the formal model for hardware components.
• 💀 jhdl - ?-2017, C++ Verilog/VHDL -> systemC, prototype
• Kactus2 - IP-core packager
• kratos - C++/Python, hardware generator/simulator
• lgraph - C, generic graph library
• llhd - Rust, HCL
• livehd - mainly C++, An infrastructure designed for Live Hardware Development.
• Lucid HDL in Alchitry-Labs - Custom language and IDE inspired by Verilog
• magma - 2017-?, Python, HCL
• migen - 2013-?, Python, HCL
• mockturtle - logic network library
• moore - Rust, HDL -> model compiler
• MyHDL - 2004-?, Python, Process based HDL
• nmigen -, Python, A refreshed Python toolbox for building complex digital hardware
• OpenTimer - , C++, A High-Performance Timing Analysis Tool for VLSI Systems
• percy - Collection of different synthesizers and exact synthesis methods for use in applications such as circuit resynthesis and design exploration.
• PyChip-py-hcl - , Python, Chisel3 like HCL
• pygears - , Python, function style HDL generator
• PyMTL3 2018-?
• PyMTL - 2014-?, Python, Process based HDL
• PipelineC - 2018-?, Python, C++ HLS-like automatic pipelining as a language construct/compiler
• PyRTL - 2015-?, Python, HCL
• Pyverilog - 2013-? Python-based Hardware Design Processing Toolkit for Verilog HDL
• rogue , C++/Python - Hardware Abstraction & Data Acquisition System
• sail 2018-?, (OCaml, Standard ML, Isabelle) - architecture definition language
• spatial - Scala, an Argon DSL like, high level abstraction
• SpinalHDL - 2015-?, Scala, HCL
• Silice - ?, C++, Custom HDL
• 💀 SyDpy - ?-2016, Python, HCL and verif. framework operating on TML/RTL level
• systemrdl-compiler - Python,c++, register description language compiler
• UHDM - C++ SystemVerilog -> C++ model
• 💀 Verilog.jl - 2017-2017, Julia, simple Julia to Verilog transpiler
• veriloggen - 2015-?, Python, Verilog centric HCL with HLS like features
• 💀 wyre - 2020-2020, Mupad, Minimalistic HDL
• phi - 2019-?, custom language, llvm based compiler of custom hdl
• prga - 2019-?. Python, prototyping platform with integrated yosys

See the sidebar for various pages.

• About PyHCL
• Data types
• Examples
• Getting Stated