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Analysis
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[SchedulingAnalysis] Support scf::IfOp and memref::LoadOp/StoreOp. (#2386)
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2021-12-24 10:23:22 -07:00 |
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CAPI
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[llvm] Update submodule to latest (#1589)
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2021-08-18 19:37:43 -07:00 |
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Conversion
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Preserves FIRRTL names (#3050)
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2022-05-06 22:52:10 -05:00 |
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Dialect
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[Calyx] Make `wires` op a graph region (#3057)
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2022-05-07 11:45:16 +02:00 |
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Scheduling
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[Scheduling] Add an ILP-based solver for the CyclicProblem. (#2650)
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2022-02-19 20:52:52 +01:00 |
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Transforms
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Fix func.func op lowering in --flatten-memref-calls
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2022-03-24 18:12:31 -04:00 |
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Unit
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[Moore] Add SystemVerilog types (#2699)
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2022-03-04 08:48:45 +01:00 |
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circt-opt
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Bump LLVM to 61814586 (#2758)
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2022-03-14 14:13:45 +01:00 |
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circt-reduce
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circt-reduce,firtool,llhd-sim: cleanup --help output, put options in category (#2979)
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2022-05-03 16:02:57 -05:00 |
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circt-translate
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[LLHD] remove the LLHD-specific Verilog printer.
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2021-12-08 14:01:45 -08:00 |
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firtool
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Preserves FIRRTL names (#3050)
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2022-05-06 22:52:10 -05:00 |
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handshake-runner
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Bump LLVM to 61814586 (#2758)
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2022-03-14 14:13:45 +01:00 |
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lib
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[NFC] Added newlines to the end of files
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2022-03-28 18:58:23 +03:00 |
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llhd-sim
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circt-reduce,firtool,llhd-sim: cleanup --help output, put options in category (#2979)
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2022-05-03 16:02:57 -05:00 |
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verilator
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[Verilator] Make the error check more flexible (#264)
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2020-11-20 11:37:13 -08:00 |
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CMakeLists.txt
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[FIRRTL] Fix black box directory from GCT
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2022-03-25 01:32:57 -04:00 |
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lit.cfg.py
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[Scheduling] Set up infrastructure for using OR-Tools' solvers. (#2465)
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2022-01-18 10:55:15 +01:00 |
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lit.site.cfg.py.in
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[Scheduling] Set up infrastructure for using OR-Tools' solvers. (#2465)
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2022-01-18 10:55:15 +01:00 |
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