Andrew Lenharth 6f550cb956 Preserves FIRRTL names (#3050) ... This does a simple wire preservation. This means: nodes and wires become wires if they have names names that don't start with '_' are preserved names don't block constant propgation, but do block deleting wires.		2022-05-06 22:52:10 -05:00
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AffineToStaticLogic	[StaticLogic] Add optional trip count attribute. (#2657)	2022-02-21 10:33:32 -07:00
ExportVerilog	ExportVerilog: Add lowering option to force direction/type on each port (#3046)	2022-05-06 17:43:07 -05:00
FIRRTLToHW	Preserves FIRRTL names (#3050)	2022-05-06 22:52:10 -05:00
HWToLLHD	[HW] Change module result port names to not have a %	2021-09-12 18:46:26 -07:00
HandshakeToFIRRTL	[NFC] Added newlines to the end of files	2022-03-28 18:58:23 +03:00
HandshakeToHW	[NFC] Added newlines to the end of files	2022-03-28 18:58:23 +03:00
LLHDToLLVM	Bump LLVM to 761bc83af4ee70c6c5156f73ed88947a5d9f013f	2022-02-16 23:32:32 -06:00
MooreToCore	[Moore] Add shift expressions (#2812)	2022-03-30 09:30:50 +02:00
SCFToCalyx	[SCFToCalyx] Add source location metadata for Cider. (#2959)	2022-05-05 09:43:19 -07:00
StandardToHandshake	[StandardToHandshake] Fix function type for external FuncOps (#2987)	2022-04-27 17:17:27 +02:00
StandardToStaticLogic	Bump LLVM to 761bc83af4ee70c6c5156f73ed88947a5d9f013f	2022-02-16 23:32:32 -06:00