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[Calyx] Make `wires` op a graph region (#3057) 

Since we can emit `comb` logic in the `wires` region of a component, I'd also expect backedges to be legal.
This commit is contained in:
Morten Borup Petersen 2022-05-07 11:45:16 +02:00 committed by GitHub
parent 6f550cb956
commit 7cc63a4db0
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2 changed files with 12 additions and 1 deletions
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9
include/circt/Dialect/Calyx/CalyxStructure.td
View File

@ -168,7 +168,8 @@ def ComponentOp : CalyxOp<"component", [
def WiresOp : CalyxContainer<"wires", [
HasParent<"ComponentOp">,
SymbolTable /* contains GroupInterface names. */
SymbolTable /* contains GroupInterface names. */,
RegionKindInterface
]> {
let summary = "Calyx Wires";
let description = [{
@ -190,6 +191,12 @@ def WiresOp : CalyxContainer<"wires", [
region->push_back(new Block());
}]>
];
let extraClassDeclaration = [{
/// Implement RegionKindInterface.
static RegionKind getRegionKind(unsigned index) { return RegionKind::Graph; }
}];
let hasVerifier = 1;
}

4
test/Dialect/Calyx/round-trip.mlir
View File

@ -55,9 +55,13 @@ calyx.program "main" {
// CHECK: calyx.assign %not.in = %r2.out : i1
// CHECK-NEXT: calyx.assign %gt.left = %r2.out ? %adder.out : i8
// CHECK-NEXT: calyx.assign %gt.left = %not.out ? %adder.out : i8
// CHECK-NEXT: calyx.assign %r.in = %0 ? %c0_i8 : i8
// CHECK-NEXT: %0 = comb.and %true, %true : i1
calyx.assign %not.in = %r2.out : i1
calyx.assign %gt.left = %r2.out ? %adder.out : i8
calyx.assign %gt.left = %not.out ? %adder.out : i8
calyx.assign %r.in = %0 ? %c0_i8 : i8
%0 = comb.and %c1_i1, %c1_i1 : i1
// CHECK: calyx.group @Group1 {
calyx.group @Group1 {