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[Verilator] Make the error check more flexible (#264) 

Verilator changed its error reporting message format since 4.0 to
include the column number. This change is to make the tests backwards
compatible to 4.028 (at least).
This commit is contained in:
John Demme 2020-11-20 11:37:13 -08:00 committed by GitHub
parent 8a6d010f6b
commit 5225d65e9f
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1 changed files with 2 additions and 2 deletions
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test/verilator/errors1.sv
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@ -7,7 +7,7 @@
module main(
input logic clk,
input wire rst_n,
// CHECK: %Warning-UNUSED: {{.*}}:9:14: Signal is not used: 'rst_n'
// CHECK: %Warning-UNUSED: {{.*}}:9{{.*}} Signal is not used: 'rst_n'
output logic [15:0] x
);
@ -16,6 +16,6 @@ module main(
always@(posedge clk) begin
x_int = x_int + 1;
// CHECK: %Warning-BLKSEQ: {{.*}}:18:11: Blocking assignments (=) in sequential (flop or latch) block
// CHECK: %Warning-BLKSEQ: {{.*}}:18{{.*}} Blocking assignments (=) in sequential (flop or latch) block
end
endmodule