f7cd3cba7a
Fix mypy errors + formatting
2023-05-17 22:19:17 -07:00
fab8c26703
Generalize XDMA driver
2023-05-17 21:55:52 -07:00
761e4d36ae
Merge remote-tracking branch 'origin' into ntnu-extended
2023-05-15 14:37:21 -07:00
b000772990
Bump to latest rocketchip
2023-05-14 16:35:39 -07:00
b08ce56202
Fix formatting
2023-05-13 10:35:51 -07:00
d9afa05df9
Revert some files | Delete old files
2023-05-12 21:28:27 -07:00
ee9ca40f50
More U250/U280 Fixes
2023-05-12 21:23:55 -07:00
d5c8f3edc3
Revert "Merge remote-tracking branch 'origin/fix-trigger-system-common-case-perf' into vcu118"
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This reverts commit 2a10f3e9af375435ec47
2023-05-12 14:20:27 -07:00
2a10f3e9af
Merge remote-tracking branch 'origin/fix-trigger-system-common-case-perf' into vcu118
2023-05-11 10:11:22 -07:00
375435ec47
Merge remote-tracking branch 'origin/main' into vcu118
2023-05-11 10:10:36 -07:00
da63aae5de
Merge remote-tracking branch 'origin/main' into fix-trigger-system-common-case-perf
2023-05-11 09:48:35 -07:00
e2a1766bc9
Merge pull request #1458 from firesim/buildbitstream-cis
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Buildbitstream CI
2023-05-11 09:46:43 -07:00
2e77fb0ffb
Merge remote-tracking branch 'origin/main' into vcu118
2023-05-11 08:24:26 -07:00
cdc2c869fd
fix TraceRV trigger performance regression for common case where trigger is permanently true or false
2023-05-11 08:22:31 -07:00
21928f7e8d
Rename .ini -> .yaml
2023-05-11 00:24:55 -07:00
cccf19138e
fix main.o build dependency on generated const.h
2023-05-10 14:31:55 -07:00
4f10f91555
Merge remote-tracking branch 'origin/main' into vcu118
2023-05-10 11:48:44 -07:00
966e09907c
Merge pull request #1500 from firesim/renameserial
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Rename SerialBridge to TSIBridge
2023-05-10 11:37:26 -07:00
0c1a7a6339
Merge pull request #1471 from firesim/bump-verilator
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Bump Verilator to 5.006
2023-05-09 13:12:44 -07:00
73ad11a969
Fix tsibridge cc/h linting
2023-05-09 10:47:49 -07:00
5f9bf2b42b
Rename SerialBridge to TSIBridge
2023-05-08 15:21:38 -07:00
872c99e827
cleanup
2023-05-08 13:53:07 -07:00
84bf370c87
Merge remote-tracking branch 'origin/ntnu-integration' into vcu118
2023-05-08 13:48:17 -07:00
5aa5c255a5
both mem channels working
2023-05-08 13:42:46 -07:00
b99c0bfcc0
Small CI fixes
2023-05-07 21:50:11 -07:00
779f9a9b51
Try new clang-format ci check | Fix Scala test path
2023-05-07 20:50:43 -07:00
33578662d3
Merge remote-tracking branch 'og/main' into ntnu-integration
2023-05-07 16:50:50 -07:00
5999fbec14
Merge pull request #1474 from firesim/fix-scala-test
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Fix Scala test on machines with multiple simulators
2023-05-07 16:18:57 -07:00
a4a7811298
Merge remote-tracking branch 'origin/ntnu-integration' into vcu118
2023-05-06 18:39:04 -07:00
4646a90832
fixes
2023-05-06 18:38:47 -07:00
49392505f6
Fix some CI issues
2023-05-06 17:56:45 -07:00
fa882bc8ad
Fix Makefile paths
2023-05-06 17:30:34 -07:00
d6de4ab565
vcu118 support throughout firesim
2023-05-06 17:09:18 -07:00
f6fc4ccfec
Intermediate changes [ci skip]
2023-05-04 23:35:56 -07:00
c231ca15f4
First attempt at bare Xilinx U250 support
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Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: Björn Gottschall <info@gottschall.no>
Co-authored-by: David Metz <david.c.metz@ntnu.no>
2023-05-03 01:07:15 -07:00
53c7bcaf40
update assert in timingmodel to allow BURST_FIXED w/len=0
2023-04-27 23:46:44 +00:00
6f2175635a
Bump to chisel 3.5.6
2023-04-05 19:22:06 -07:00
a4a36ca6ce
Update package for config
2023-04-05 19:22:06 -07:00
6fb10976ab
Update Makefile to be non-parallel
2023-03-30 05:39:53 -07:00
4d54d40122
Merge remote-tracking branch 'origin/main' into local-fpga-docs
2023-03-21 23:07:46 -07:00
66fce79be5
Fix duplicated testnames if running on machine with both VCS/Verilator
2023-03-18 14:48:18 -07:00
18d68946f3
Change to C++20, Fix clock gating in Verilator
2023-03-18 12:39:44 -07:00
0e77b74a1a
Expand TracerV to support more than 7 IPC ( #1383 )
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TracerV now uses a variable number of beats to send traces over to C++. This allows FireSim and TracerV to work with cores that have more than 7 IPC.
2023-03-13 09:36:23 -07:00
cbfc9a6430
Merge remote-tracking branch 'origin/main' into local-fpga-docs
2023-03-11 15:49:21 -08:00
ab9adbc77d
Merge pull request #1466 from firesim/bump-chipyard
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Bump Chipyard + Update Vitis Xclbin + AWS AGFIs
2023-03-11 14:09:50 -08:00
d91d8049d9
Fix clang comment
2023-03-10 22:33:20 +00:00
90420d58e2
Rework comment
2023-03-10 21:54:06 +00:00
159e949e6d
Fix forward progress in driver | Add more checks for correct profile-interval
2023-03-10 18:50:51 +00:00
e209b89b97
Update .gitignore for .ivy2/.sbt
2023-03-09 19:59:06 -08:00
5d979ed4bd
Revert to UInt64 for offsetConst in SerialBridge
2023-03-08 18:07:02 -08:00
69e428f010
Local .ivy2/.sbt
2023-03-05 22:39:45 -08:00
d826776d6c
Update docs w/ fixes
2023-03-05 17:40:33 -08:00
2f13158e0e
Initial support for fat jars
2023-03-03 17:17:16 -08:00
31049aae1e
Remove SBT thin client
2023-03-02 23:18:28 -08:00
a81e3725c1
Removed test_harness_bridge and simplified harnesses ( #1442 )
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* Removed test_harness_bridge and simplified harnesses
Instead, the test is now performed by `fasedtests_top`, in line with other tests.
Also slightly simplified the test harnessed for both FASED and FireSim.
* Update sim/midas/src/main/cc/core/systematic_scheduler.h
Co-authored-by: David Biancolin <david.biancolin@sifive.com>
---------
Co-authored-by: David Biancolin <david.biancolin@sifive.com>
2023-03-01 23:42:43 +00:00
22143b6580
Bump SBT to 1.8.2
2023-02-28 17:32:33 -08:00
c7dbbe2724
Move bridge init/finish handling into the simulation base ( #1441 )
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The changes exposed a problem in the `AXI4Buffer` done signal. To avoid relying on latencies,
the done signal is now gated with reset.
2023-02-28 23:44:04 +00:00
38a02b3b90
Converted FASEDMemoryTimingModel into a bridge ( #1440 )
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This PR slightly cleans up the bridge interface by provding default implementation of the methods.
The FASED bridge is now a full bridge and requires no special handling in the widget registry.
De-duplicating initialisation/finalization logic in harnesses.
2023-02-28 19:47:14 +00:00
e0569ff124
Fix replace-rtl ordering problem ( #1444 )
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Not all sub-rules build the directory and replace-rtl failed if trying to copy the driver first.
2023-02-28 17:01:46 +02:00
0755382dae
Extends tests to work with post-synth RTL ( #1439 )
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Includes improvements to post-synth simulations:
- Added a `QUICK` strategy which tries to get Vivado to run fast, yet still helps us reproduce failures
- Limited Vivado to 1 thread to mitigate flakyness from parallel synthesis
- The harness now explicitly waits for GSR
- Integrated post-synth metasims with the harness. Setting `TEST_DISABLE_VIVADO=1` in the environment disables these tests even if Vivado is available.
Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-27 18:20:01 +02:00
fc759f29f1
VCS post-synthesis RTL simulators ( #1438 )
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This PR adds make rules to get the post-synth RTL out of vivado and build a VCS simulator out of it.
On VCS, a 150ns startup delay is hard-wired on all simulation modes to yield identical waveforms.
The delay is required to initialize vivado gate-level libraries.
Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-24 08:06:50 +02:00
6e993f5089
Fix wiring of unused ports ( #1437 )
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A previous PR set the values to 0, which is incorrect, however CI auto-merged the changes without blocking on the failure.
2023-02-22 10:57:29 +00:00
4b5840fca8
Do not materialize memory connections if the target does not use them ( #1431 )
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In line with the omission of managed stream engines and their associated connections
to the top-level, this PR also eliminates unused memory connections. The top-level
ports to the platform hardware are left unchanged. If no memories are used in the
target, the `LoadMem` widget is omitted.
2023-02-21 18:45:38 +00:00
84b1c3f900
Add option to F1 driver to load an AGFI ( #1434 )
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If the `+agfi=` option points to an AGFI, the image is loaded before the simulation starts.
2023-02-21 19:00:34 +02:00
797e6e41bc
Introduced a full verilator/vcs/debug matrix ( #1435 )
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This PR moves the paramterization of test harnesses to the toplevel.
Slightly re-wrote tests to avoid duplication of running logic.
2023-02-19 11:31:03 +00:00
9818dbcae3
Added a test for memory accesses ( #1433 )
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This PR fixes the invocation to `LoadMem` and adds a test for it.
The test performs memory read accesses through a TileLink node which goes to DRAM through a trivial FASED bridge.
Read requests from the driver are received through the `PeekPokeBridge` and are sent back to be printed to a file.
The test harness compares the file passed to loadmem with the results produced by this bridge, which should read all data back.
2023-02-18 20:14:42 +02:00
c6f72296aa
Do not materialize a stream engine if no streams are used ( #1430 )
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The stream engine is omitted from the design and the driver if there are no bridges relying on it.
This is very useful for debugging as it eliminates a lot of SystemVerilog generated from most small
designs and reduces the amount of gates synthesized for smaller tests.
2023-02-11 09:37:30 +02:00
bec25aaf19
Tests for existing TracerV bridge including trigger modes ( #1426 )
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* Tests for mode 0,1,2
* Test for mode 3 disabled until Issue #1428 is resolved
2023-02-09 11:40:04 -08:00
d194593ece
Enabled scalafmt on more sources ( #1429 )
2023-02-09 09:25:39 -08:00
30fd72bc7f
Remove `constructor.h` and replace it with a Scala-generated header ( #1398 )
2023-02-08 00:52:51 +02:00
abed23be29
Restored the runtime config generation phase ( #1425 )
2023-02-03 09:06:04 +02:00
6420252509
Removed auxiliary functions from simif_t ( #1424 )
2023-02-02 22:25:40 +02:00
9d3462ed13
Merge pull request #1392 from firesim/scala213
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Bump to latest rocket-chip/scala2.13
2023-02-01 14:30:09 -08:00
bf051c785f
Re-enabled timeout detection for harnesses ( #1423 )
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The changes got lost in rebases. This PR re-introduces them.
2023-02-01 19:21:02 +00:00
2889818e7d
Removed the compiler-generated runtime config ( #1422 )
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The default arguments to FASED memory models are now passed alongside other FASED bridge arguments.
These defaults can be overriden by other args passed to the bridge driver or disabled when the raw hardware configuration is requested.
The manager can still pass an optional runtime config to the design to override arguments.
2023-02-01 19:19:00 +02:00
9ae4ed7f52
Passed memory offsets to genHeader ( #1416 )
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Instead of emitting a constant and referencing it by name in the header for
a bridge constructor, the memory mapping is passed alongside the base offset
for MMIO for bridge header emission to reference.
2023-02-01 10:47:14 +00:00
4d1876334e
Introduced a unique main to the simulation. ( #1368 )
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The main method centralizes more of the lifecycle of a simulation.
2023-02-01 10:40:08 +02:00
2a5f0cfe70
Revert changing testOnly behavior
2023-01-30 23:30:17 -08:00
a1981c11ec
Merge remote-tracking branch 'origin/main' into scala213
2023-01-30 17:24:06 -08:00
9bebd0a294
Bump CI log tail length to 300 lines
2023-01-30 14:16:20 -08:00
b191677aa4
Fix undriven signals in BlockDevDUT
2023-01-30 09:39:23 -08:00
0c2e8dd6bc
Fixed missing array include ( #1417 )
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Some versions of GCC/Clang complain, some do not. This includes the header.
2023-01-30 08:24:32 +02:00
7af5bd9f67
Run Scala formatting
2023-01-27 13:52:18 -08:00
a6de5dd121
Fix midas AutoILA to not depend on set traversal ordering
2023-01-27 13:52:18 -08:00
96ef6200fe
Bump chipyard.mk to scala 2.13
2023-01-27 13:52:18 -08:00
d384fc52bc
Fix testOnly rule
2023-01-27 13:52:18 -08:00
0882cc2715
Fix AXI4Tieoff missing import
2023-01-27 13:52:18 -08:00
3670816922
Bump scalafix
2023-01-27 13:52:18 -08:00
697b5a59d9
Remaining fixes to bump to scala 2.13
2023-01-27 13:52:18 -08:00
a560cd1b8e
Bump to scala 2.13/chisel 3.5.5
2023-01-27 13:52:18 -08:00
ad7d0f009e
Fix drivers
2023-01-27 18:00:48 +00:00
240875234d
Fix Vitis driver compile | Fix CY-as-top issues
2023-01-27 18:00:48 +00:00
6d39766d6d
Fix incremental builds triggered by scala changes ( #1408 )
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Fixed the DRY'd grep pattern. Incremental builds should work now.
2023-01-26 09:56:13 -08:00
0b8289acd8
Merge pull request #1401 from firesim/jerryz123-patch-3
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Fix loadmem bug in firesim_tsi.cc
2023-01-25 16:48:15 -08:00
1b03338a47
Update sim/firesim-lib/src/main/cc/fesvr/firesim_tsi.h
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Co-authored-by: David Biancolin <david.biancolin@sifive.com>
2023-01-25 14:20:37 -08:00
56790ead95
Merge pull request #1396 from firesim/add-vcs-metasims
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Add VCS metasimulation to CI
2023-01-25 11:14:52 -08:00
a513c0ef58
Add scalaFix ( #1393 )
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* adding scalaFix to the projecting, using two make targets, `scala-lint` and `scala-lint-check`
* adding documentation
Co-authored-by: David Biancolin <david.biancolin@sifive.com>
2023-01-25 10:34:10 -08:00
cdb46619d9
Moved simulation step control to the PeekPoke bridge ( #1399 )
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The STEP and DONE fields of the simulation master were fully determined by the behaviour of the peek poke bridge.
Since that stepping logic is closely tied to peek-poke logic, this PR moves it into that bridge.
Temporarily, the `firesim_top` harness now uses PeekPoke to drive the simulation. This will be removed in a future PR.
2023-01-25 19:12:44 +02:00
64ea141ecc
Fix bug in fesvr loadmem path
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chunk_align has to match the loadmem-DRAM interface width
Hardcode this for now
2023-01-24 15:45:53 -08:00
c2204d6593
Added a bridge registry to own all bridge instances ( #1369 )
2023-01-24 23:08:59 +00:00
abejgonzalez