Change to C++20, Fix clock gating in Verilator

sim/make/cpp-lint.mk

@@ -26,7 +26,7 @@ clang_tidy_flags :=\
 	-I$(firesim_base_dir)/firesim-lib/src/main/cc \
 	-I$(firesim_base_dir)/src/main/cc/midasexamples \
 	-I$(testchipip_csrc_dir) \
-	-std=c++17 \
+	-std=c++20 \
 	-x c++
 
 # Checks the files in parallel without applying fixes.

sim/make/verilator.mk

@@ -4,7 +4,7 @@
 # Verilator MIDAS-Level Simulators #
 ####################################
 
-VERILATOR_CXXOPTS ?= -O0
+VERILATOR_CXXOPTS ?= -O2
 VERILATOR_MAKEFLAGS ?= -j8 VM_PARALLEL_BUILDS=1
 
 verilator = $(GENERATED_DIR)/V$(DESIGN)

sim/midas/src/main/cc/Makefile

@@ -52,18 +52,7 @@ $(OUT_DIR)/$(DRIVER_NAME)-$(PLATFORM): $(DRIVER) $(driver_h) $(platform_o) $(bri
 driver: $(OUT_DIR)/$(DRIVER_NAME)-$(PLATFORM)
 
 # Sources for building MIDAS-level simulators. Must be defined before sources VCS/Verilator Makefrags
-override CXXFLAGS += -std=c++17 -include $(design_h)
-# Force verilator to obey our -std=c++17 from CXXFLAGS if it thinks it needs to add a -std argument to the compiler
-# by default, it will capture a -std argument during it's build using heuristics to try and match
-# the system-package for SystemC.
-# 1. we don't use SystemC
-# 2. the heuristics Verilator uses to capture -std at configure are incorrect for us
-# 3. Verilator output compiles and links for us fine with std=c++17
-# VERILATOR_FLAGS could do this with
-#   VERILATOR_FLAGS += -MAKEFLAGS CFG_CXXFLAGS_STD_NEWEST=
-# but we don't pass --build to it, we invoke the make build ourselves
-# see also https://github.com/verilator/verilator/issues/3588
-VERILATOR_MAKEFLAGS += CFG_CXXFLAGS_STD_NEWEST=
+override CXXFLAGS += -std=c++20 -include $(design_h)
 
 # Models of FPGA primitives that are used in host-level sim, but not in FPGATop
 sim_fpga_resource_models := $(v_dir)/BUFGCE.v

sim/midas/src/main/cc/rtlsim/Makefrag-verilator

@@ -17,7 +17,7 @@
 #   (optional) verilator_conf: An verilator configuration file
 #   (optional) VERILATOR_FLAGS: extra flags depending on the target
 
-VERILATOR ?= verilator --cc --exe
+VERILATOR ?= verilator --cc --exe --timing
 verilator_v := $(emul_v) $(verilator_wrapper_v)
 verilator_cc := $(emul_cc) $(verilator_harness)
 
@@ -25,10 +25,15 @@ TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1
 override VERILATOR_FLAGS := \
 	$(TIMESCALE_OPTS) \
 	--top-module $(top_module) \
-	-Wno-STMTDLY \
 	-O3 \
+	-sv \
 	--output-split 10000 \
 	--output-split-cfuncs 100 \
+	-Wall \
+	-Wno-UNUSEDSIGNAL \
+	-Wno-DECLFILENAME \
+	-Wno-VARHIDDEN \
+	-Wno-UNDRIVEN \
 	-CFLAGS "$(CXXFLAGS) " \
 	-LDFLAGS "$(LDFLAGS) " \
 	$(VERILATOR_FLAGS)

sim/midas/src/main/verilog/BUFGCE.v

@@ -3,16 +3,8 @@ module BUFGCE(
   input      CE,
   output reg O
 );
-   reg       enable_latch;
-   always @(posedge I)
-     enable_latch <= CE;
-`ifdef VERILATOR
-   // Note: Verilator doesn't like procedural clock gates
-   // They cause combinational loop errors and UNOPT_FLAT
-   assign O = (I & enable_latch);
-`else
-   // Note: VCS doesn't like the Verilator clock gate
-   // Delays clock edge too much when CE is a register
+   /* verilator lint_off BLKSEQ */
+   // VCS/Verilator-v5 compatible clock gating
    // Blocking assignment makes behavior deterministic
    always @(posedge I or negedge I) begin
      if (CE)
@@ -20,5 +12,5 @@ module BUFGCE(
      else
        O = 1'h0;
    end
-`endif
+   /* verilator lint_on BLKSEQ */
 endmodule