Merge pull request #1500 from firesim/renameserial
Rename SerialBridge to TSIBridge
This commit is contained in:
commit
966e09907c
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@ -11,7 +11,7 @@ Bridges enable:
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Here you instantiate bridges at the I/O boundary of your chip, to provide
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a simulation models of the environment your design is executing in. For an
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FPGA-hosted model, see FASED memory timing models. For co-simulated models
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see the UARTBridge, BlockDeviceBridge, and SerialBridge.
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see the UARTBridge, BlockDeviceBridge, and TSIBridge.
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#. **Verification against a software golden model.** Attach an bridge (anywhere
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in your target RTL) to an interface you'd like to monitor, (e.g., a
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@ -9,7 +9,7 @@ project {
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"glob:**firesim-lib/src/main/scala/bridges/BlockDevBridge.scala",
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"glob:**firesim-lib/src/main/scala/bridges/DromajoBridge.scala",
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"glob:**firesim-lib/src/main/scala/bridges/GroundTestBridge.scala",
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"glob:**firesim-lib/src/main/scala/bridges/SerialBridge.scala",
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"glob:**firesim-lib/src/main/scala/bridges/TSIBridge.scala",
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"glob:**firesim-lib/src/main/scala/bridges/SimpleNICBridge.scala",
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"glob:**firesim-lib/src/main/scala/bridges/TracerVBridge.scala",
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"glob:**firesim-lib/src/main/scala/bridges/UARTBridge.scala",
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@ -1,6 +1,6 @@
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// See LICENSE for license details
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#include "serial.h"
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#include "tsibridge.h"
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#include "bridges/loadmem.h"
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#include "core/simif.h"
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#include "fesvr/firesim_tsi.h"
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@ -8,20 +8,20 @@
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#include <cassert>
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#include <gmp.h>
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char serial_t::KIND;
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char tsibridge_t::KIND;
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serial_t::serial_t(simif_t &simif,
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loadmem_t &loadmem_widget,
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const SERIALBRIDGEMODULE_struct &mmio_addrs,
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int serialno,
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const std::vector<std::string> &args,
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bool has_mem,
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int64_t mem_host_offset)
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tsibridge_t::tsibridge_t(simif_t &simif,
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loadmem_t &loadmem_widget,
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const TSIBRIDGEMODULE_struct &mmio_addrs,
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int tsino,
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const std::vector<std::string> &args,
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bool has_mem,
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int64_t mem_host_offset)
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: bridge_driver_t(simif, &KIND), mmio_addrs(mmio_addrs),
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loadmem_widget(loadmem_widget), has_mem(has_mem),
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mem_host_offset(mem_host_offset) {
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std::string num_equals = std::to_string(serialno) + std::string("=");
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std::string num_equals = std::to_string(tsino) + std::string("=");
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std::string prog_arg = std::string("+prog") + num_equals;
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std::vector<std::string> args_vec;
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args_vec.push_back("firesim_tsi");
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@ -56,7 +56,7 @@ serial_t::serial_t(simif_t &simif,
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}
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// debug for command line arguments
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printf("command line for program %d. argc=%d:\n", serialno, argc_count);
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printf("command line for program %d. argc=%d:\n", tsino, argc_count);
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for (int i = 0; i < argc_count; i++) {
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printf("%s ", tsi_argv[i + 1]);
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}
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@ -65,7 +65,7 @@ serial_t::serial_t(simif_t &simif,
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tsi_argc = argc_count + 1;
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}
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serial_t::~serial_t() {
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tsibridge_t::~tsibridge_t() {
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delete fesvr;
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if (tsi_argv) {
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for (int i = 0; i < tsi_argc; ++i) {
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@ -75,7 +75,7 @@ serial_t::~serial_t() {
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}
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}
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void serial_t::init() {
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void tsibridge_t::init() {
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// `ucontext` used by tsi cannot be created in one thread and resumed in
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// another. To ensure that the tsi process is on the correct thread, it is
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// built here, as the bridge constructor may be invoked from a thread other
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@ -85,23 +85,23 @@ void serial_t::init() {
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go();
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}
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void serial_t::go() { write(mmio_addrs.start, 1); }
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void tsibridge_t::go() { write(mmio_addrs.start, 1); }
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void serial_t::send() {
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void tsibridge_t::send() {
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while (fesvr->data_available() && read(mmio_addrs.in_ready)) {
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write(mmio_addrs.in_bits, fesvr->recv_word());
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write(mmio_addrs.in_valid, 1);
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}
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}
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void serial_t::recv() {
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void tsibridge_t::recv() {
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while (read(mmio_addrs.out_valid)) {
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fesvr->send_word(read(mmio_addrs.out_bits));
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write(mmio_addrs.out_ready, 1);
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}
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}
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void serial_t::handle_loadmem_read(firesim_loadmem_t loadmem) {
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void tsibridge_t::handle_loadmem_read(firesim_loadmem_t loadmem) {
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assert(loadmem.size % sizeof(uint32_t) == 0);
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assert(has_mem);
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// Loadmem reads are in granularities of the width of the FPGA-DRAM bus
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@ -133,7 +133,7 @@ void serial_t::handle_loadmem_read(firesim_loadmem_t loadmem) {
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fesvr->tick();
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}
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void serial_t::handle_loadmem_write(firesim_loadmem_t loadmem) {
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void tsibridge_t::handle_loadmem_write(firesim_loadmem_t loadmem) {
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assert(loadmem.size <= 1024);
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assert(has_mem);
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static char buf[1024];
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@ -152,7 +152,7 @@ void serial_t::handle_loadmem_write(firesim_loadmem_t loadmem) {
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mpz_clear(data);
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}
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void serial_t::serial_bypass_via_loadmem() {
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void tsibridge_t::tsi_bypass_via_loadmem() {
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firesim_loadmem_t loadmem;
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while (fesvr->has_loadmem_reqs()) {
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// Check for reads first as they preceed a narrow write;
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@ -163,7 +163,7 @@ void serial_t::serial_bypass_via_loadmem() {
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}
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}
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void serial_t::tick() {
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void tsibridge_t::tick() {
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// First, check to see step_size tokens have been enqueued
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if (!read(mmio_addrs.done))
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return;
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@ -174,7 +174,7 @@ void serial_t::tick() {
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fesvr->tick();
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}
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if (fesvr->has_loadmem_reqs()) {
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serial_bypass_via_loadmem();
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tsi_bypass_via_loadmem();
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}
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if (!terminate()) {
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// Write all the requests to the target
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@ -183,5 +183,5 @@ void serial_t::tick() {
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}
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}
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bool serial_t::terminate() { return fesvr->done(); }
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int serial_t::exit_code() { return fesvr->exit_code(); }
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bool tsibridge_t::terminate() { return fesvr->done(); }
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int tsibridge_t::exit_code() { return fesvr->exit_code(); }
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@ -1,6 +1,6 @@
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// See LICENSE for license details
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#ifndef __SERIAL_H
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#define __SERIAL_H
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#ifndef __TSIBRIDGE_H
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#define __TSIBRIDGE_H
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#include "bridges/serial_data.h"
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#include "core/bridge_driver.h"
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@ -9,7 +9,7 @@ class loadmem_t;
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class firesim_tsi_t;
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class firesim_loadmem_t;
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struct SERIALBRIDGEMODULE_struct {
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struct TSIBRIDGEMODULE_struct {
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uint64_t in_bits;
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uint64_t in_valid;
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uint64_t in_ready;
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@ -21,26 +21,26 @@ struct SERIALBRIDGEMODULE_struct {
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uint64_t start;
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};
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class serial_t : public bridge_driver_t {
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class tsibridge_t : public bridge_driver_t {
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public:
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/// The identifier for the bridge type used for casts.
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static char KIND;
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serial_t(simif_t &simif,
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loadmem_t &loadmem_widget,
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const SERIALBRIDGEMODULE_struct &mmio_addrs,
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int serialno,
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const std::vector<std::string> &args,
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bool has_mem,
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int64_t mem_host_offset);
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~serial_t();
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tsibridge_t(simif_t &simif,
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loadmem_t &loadmem_widget,
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const TSIBRIDGEMODULE_struct &mmio_addrs,
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int tsino,
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const std::vector<std::string> &args,
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bool has_mem,
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int64_t mem_host_offset);
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~tsibridge_t();
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virtual void init();
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virtual void tick();
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virtual bool terminate();
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virtual int exit_code();
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private:
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const SERIALBRIDGEMODULE_struct mmio_addrs;
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const TSIBRIDGEMODULE_struct mmio_addrs;
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loadmem_t &loadmem_widget;
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firesim_tsi_t *fesvr;
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@ -63,7 +63,7 @@ private:
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// Helper functions to handoff fesvr requests to the loadmem unit
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void handle_loadmem_read(firesim_loadmem_t loadmem);
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void handle_loadmem_write(firesim_loadmem_t loadmem);
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void serial_bypass_via_loadmem();
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void tsi_bypass_via_loadmem();
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};
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#endif // __SERIAL_H
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#endif // __TSIBRIDGE_H
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@ -7,53 +7,52 @@ import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config.Parameters
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import testchipip.{SerialIO, SerialAdapter}
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import testchipip.{TSIIO, TSI}
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/**
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* Class which parameterizes the SerialBridge
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* Class which parameterizes the TSIBridge
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*
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* memoryRegionNameOpt, if unset, indicates that firesim-fesvr should not attempt to write a payload into DRAM through the loadmem unit.
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* This is suitable for target designs which do not use the FASED DRAM model.
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* If a FASEDBridge for the backing AXI4 memory is present, then memoryRegionNameOpt should be set to the same memory region name which is passed
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* to the FASEDBridge. This enables fast payload loading in firesim-fesvr through the loadmem unit.
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*/
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case class SerialBridgeParams(memoryRegionNameOpt: Option[String])
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case class TSIBridgeParams(memoryRegionNameOpt: Option[String])
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class SerialBridge(memoryRegionNameOpt: Option[String]) extends BlackBox with Bridge[HostPortIO[SerialBridgeTargetIO], SerialBridgeModule] {
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val io = IO(new SerialBridgeTargetIO)
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class TSIBridge(memoryRegionNameOpt: Option[String]) extends BlackBox with Bridge[HostPortIO[TSIBridgeTargetIO], TSIBridgeModule] {
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val io = IO(new TSIBridgeTargetIO)
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val bridgeIO = HostPort(io)
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val constructorArg = Some(SerialBridgeParams(memoryRegionNameOpt))
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val constructorArg = Some(TSIBridgeParams(memoryRegionNameOpt))
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generateAnnotations()
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}
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object SerialBridge {
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def apply(clock: Clock, port: SerialIO, memoryRegionNameOpt: Option[String], reset: Bool)(implicit p: Parameters): SerialBridge = {
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val ep = Module(new SerialBridge(memoryRegionNameOpt))
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ep.io.serial <> port
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object TSIBridge {
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def apply(clock: Clock, port: TSIIO, memoryRegionNameOpt: Option[String], reset: Bool)(implicit p: Parameters): TSIBridge = {
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val ep = Module(new TSIBridge(memoryRegionNameOpt))
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ep.io.tsi <> port
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ep.io.clock := clock
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ep.io.reset := reset
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ep
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}
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}
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class SerialBridgeTargetIO extends Bundle {
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val serial = Flipped(new SerialIO(SerialAdapter.SERIAL_TSI_WIDTH))
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class TSIBridgeTargetIO extends Bundle {
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val tsi = Flipped(new TSIIO)
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val reset = Input(Bool())
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val clock = Input(Clock())
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}
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class SerialBridgeModule(serialBridgeParams: SerialBridgeParams)(implicit p: Parameters)
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extends BridgeModule[HostPortIO[SerialBridgeTargetIO]]()(p) {
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class TSIBridgeModule(tsiBridgeParams: TSIBridgeParams)(implicit p: Parameters)
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extends BridgeModule[HostPortIO[TSIBridgeTargetIO]]()(p) {
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lazy val module = new BridgeModuleImp(this) {
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val io = IO(new WidgetIO)
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val hPort = IO(HostPort(new SerialBridgeTargetIO))
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val hPort = IO(HostPort(new TSIBridgeTargetIO))
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val serialBits = SerialAdapter.SERIAL_TSI_WIDTH
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val inBuf = Module(new Queue(UInt(serialBits.W), 16))
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val outBuf = Module(new Queue(UInt(serialBits.W), 16))
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val inBuf = Module(new Queue(UInt(TSI.WIDTH.W), 16))
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val outBuf = Module(new Queue(UInt(TSI.WIDTH.W), 16))
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val tokensToEnqueue = RegInit(0.U(32.W))
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val target = hPort.hBits.serial
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val target = hPort.hBits.tsi
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val tFire = hPort.toHost.hValid && hPort.fromHost.hReady && tokensToEnqueue =/= 0.U
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val targetReset = tFire & hPort.hBits.reset
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inBuf.reset := reset.asBool || targetReset
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@ -90,16 +89,16 @@ class SerialBridgeModule(serialBridgeParams: SerialBridgeParams)(implicit p: Par
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genCRFile()
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override def genHeader(base: BigInt, memoryRegions: Map[String, BigInt], sb: StringBuilder): Unit = {
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val memoryRegionNameOpt = serialBridgeParams.memoryRegionNameOpt
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val memoryRegionNameOpt = tsiBridgeParams.memoryRegionNameOpt
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val offsetConst = memoryRegionNameOpt.map(memoryRegions(_)).getOrElse(BigInt(0))
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genConstructor(
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base,
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sb,
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"serial_t",
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"serial",
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"tsibridge_t",
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"tsibridge",
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Seq(
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CppBoolean(serialBridgeParams.memoryRegionNameOpt.isDefined),
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CppBoolean(tsiBridgeParams.memoryRegionNameOpt.isDefined),
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UInt64(offsetConst)
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),
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hasLoadMem = true
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@ -14,7 +14,7 @@ clang_tidy_files := $(shell \
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| grep -v simif_ \
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| grep -v tracerv \
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| grep -v dromajo \
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| grep -v serial \
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| grep -v tsibridge \
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| grep -v fesvr \
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| grep -v generated-src \
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| grep -v output \
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@ -17,7 +17,7 @@ DRIVER_CC := \
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$(testchipip_csrc_dir)/testchip_tsi.cc \
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$(wildcard $(addprefix $(firesim_lib_dir)/, \
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bridges/uart.cc \
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bridges/serial.cc \
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bridges/tsibridge.cc \
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bridges/blockdev.cc \
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bridges/tracerv.cc \
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fesvr/firesim_tsi.cc \
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@ -1 +1 @@
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Subproject commit 3b303ba37d3a9f197ca1cb1b4865649f7b586cb8
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Subproject commit eced8e63d9171d5b03c50ac1503ba54fa18ef002
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