We would like to be able to tell what the pre- and post-link circuit
paths of the design are going to be without having to elaborate the
`PlatformShim` to get at the corresponding `XDCPathToCircuitAnnotation`.
This commit adds the two new config options `PreLinkCircuitPath` and
`PostLinkCircuitPath`, and moves the platform-specific paths out from
`F1Shim` and `VitisShim` and into the corresponding `F1Config` and
`VitisConfig`, respectively. This allows other parts of the codebase to
determine these paths purely from the config. Since the platform-
specific shim code now no longer has to specify these paths directly,
the `SpecifyXDCCircuitPaths` is moved up into the parent `PlatformShim`
class which annotates the paths provided by the config.
Eliminated ChLeafType and allowed pipe channels to carry arbitrary bundles.
In SimWrapper, pipe channels can be built from multiple reference targets.
When pipe channels are built by bridges, the logic is unchanged and bundles
are still split into their constituent channels to avoid any performance
degradation that might arise from the additional coupling.
* Put instPath before label in AutoCounter output
In a design with many autocounters being output, it is often the case that the instPath can be:
* quite long
* have common substrings across many of the counters
To simplify post-processing, it is strongly preferred that the instPath is first so that common prefix algorithms
can be used to shorten the autocounter labels.
I think @davidbiancolin has other people who have complained about the consistency of name ordering
in other places as well.
* Fixup validation name generator as well.
This patch moves the materialization of FCCAs connected to bridges to the BridgeExtraction stage.
Up to that point, information about channels connected to bridges is carried in the bridgeChannels field of the SerializableBridgeAnnotation. Bridges with IO towards the target must construct BridgeChannel decriptors
for the channels they want materialized instead of eagerly creating FCCAs.
This commit does three things:
- Add a `CustomAnnotations` test to the midasexamples test suite which
is basically the shift register test with additional uses of the
`XDC(...)` Chisel API. The test checks whether the expected files get
generated and contain the expected lines.
- Add an early out to `WriteXDCFile.formatArguments` in case the format
argument list is empty. This allows the user to specify an XDC
constraint that contains no format arguments, which until now would
cause an exception in `argumentList.head`. The end-to-end test checks
for this.
- Add type hints to the `XDCAnnotation` such that the
`XDCDestinationFile` case objects get serialized properly.
Removed the specialised clock bridge annotation to fully re-use the
functionality provided by the serializable bridge annotation.
Pattern matching now needs to verify the widget constructor name.
In-memory bridges were used to simplify the construction of bridges in 3 midas transforms.
To simplify bridge annotation representation, this patch removes them and moves all uses
over to the `widgetClass`/`widgetConstructorKey` interface. As an added benefit, this
ensures that no user can construct bridge annotations that cannot be serialized. In intermediary
`.fir` dumps, now bridge parameters show up correctly serialized.
The `Fame1Instances` transformation was used solely to clock gate the model within `FasedMemoryTimingModel`. Instead of the transformation which individually altered all memories and registers within the hierarchy, now a clock gate is used on the clock signal passed to the model.
Altered `HostSpecialization` for Xilinx to replace all modules which have `AbstractClockGate` in their name since the elaboration of the simulation wrapper generates the `AbstractClockGate_0` name to avoid duplication.
In `mm.c`, memory mappings are now created using `MAP_NORESERVE`.
By default, the call attempts to allocate petabytes, failing eagerly on some systems.
With `MAP_NORESERVE`, the oversized allocation succeeds, but a segfault occurs if
there is not enough backing physical memory as execution progresses.
Changed virtual private base class to a virtual public base class to work around a clang compilation failure. Also marked other classes final to work around virtual-related compiler warnings.
* Add no as-needed to workaround vcs link-time issues
* metasim: clean up handling of inter-context pointers
Management of master, dma mm_t structures has been a source of
considerable pain. These are globals that are used facillate
communication between the driver and RTL simulator contexts.
This commit an insidious dynamic_cast (which segfaults under modern
versions of VCS), and converts the underlying
pointers to raw pointers, to avoid double free behavior that has been
observed running under VCS at sifive.
Long term, these globals can be removed when the driver context is pushed
behind a single DPI invocation.
* makefrag: push platform-specific CXXFLAGS/LDFLAGS into driver target
* makefrag: move dead comments about libfesvr linkage
Co-authored-by: Tim Snyder <timothy.snyder@sifive.com>
newer versions of inttypes.h do not define the std C formatting
macros unless __STDC_FORMAT_MACROS is defined before inttypes.h
is included. Defining it via cmdline until we rewrite the driver
I/O to use C++.
first cut of https://anaconda.org/ucb-bar/dromajo has the
libdromajo_cosim.a but doesn't have libdromajo_cosim.h
To work around, I add the source directory back into the -I paths
for the header until the package is fixed
* Enabled clang-format on C++ sources
Ran clang-format on sources committed to the repository and added a CI job to ensure sources are properly formatted on each commit.
Clang-format can be installed using Linux package managers and the `git clang-format` command can be used to format all files that change with a commit.
* Update docs/Developer-Docs/GoldenGate-and-Driver-Development.rst
Co-authored-by: Tim Snyder <timothy.snyder@sifive.com>
* Update scripts/machine-launch-script.sh
Co-authored-by: Tim Snyder <timothy.snyder@sifive.com>
Co-authored-by: David Biancolin <david.biancolin@sifive.com>
Co-authored-by: Tim Snyder <timothy.snyder@sifive.com>
Now that printf statements are named, and thus annotatable
remove a long-standing hack that has the PrintfAnnotation label
the parameters to the statement instead of the statement itself
Verilator complains about instances of modules with no definitions that
are in the Shim and not part of the metasimulation module hierarchy.
This temporarily silences that.
* moves get_local_shared_librares into runtools.utils so that same helper
can be used for switch and driver
* stop setting LD_LIBRARY_PATH for FireSim-f1 when running, instead
add $ORIGIN to the beginning of RPATH for both driver and switch
* cleaned up a TODO that was TODONE by Sagar a long time ago
* switch makefile updated to use standard env vars (so that it is easier
to tweak the build in standard ways). The only actual change is addition
of $ORIGIN at front of rpath
There was a mixture of using CXXFLAGS and CFLAGS in the FireSim driver makefiles
this led to needing to pass both of them to VCS and Verilator. However, everything
we're building is C++ and so is Verilator, so we should only need to use CXXFLAGS.
This cuts down on the size of the compile commandlines and makes them much easier to reason about.
* Initial sim/ support for Vitis platform
* Try to make CI work nicely with local-fpga testing
* Fix MIDAS compile | Bump CY
* Remove extra pci_init | Remove extra import
* First pass at porting to python3
* Fix import errors | Setup user argcomplete
* Update awstools CLI with user data file | Bump CI to use it
* Wait until launch is complete
* Add userdata as string | Use sudo for machine-launch-script
* Remove execute permissions on machine-launch-script
* Better match on machine-launch-script complete
* Revert python-devel removal
* Use python3 for pytests
* Update more python3 items
* Remove extra shebang
* Port docs to python3 and add to CI
* Add ISCA experiments to CI build check
* Use yum not apt-get
* Add make to doc section
* Bump multilate-loadgen for sysroot fix
* For BW test build don't use shebang
* Fix docs Makefile options
* Fix more doc warnings
* Add first set of regression tests
* Fix raw_input
* Regression bump | Run workload fix
* Add functools to topology
* Fix linux poweroff test (nic still has issues)
* Update regression scripts
* Ignore machine-launch-script.sh in regression area
* Fix map python3 issues
* Get rid of shebangs
* Fix more regressions
* Print machine-launch.log on fail | More clarification on user_data
* Transfer to CI some shorter regressions
* Add a manual approval to fpga based tests
* Fix indentation in config.yml
* Fix test symlink
* Use spot for CI manager instance | Try to use python3 for aws CI container | Version all pip packages
* Make run-ini-api-tests an executable
* Fix CI terminaterunfarm arg
* Add firesim.pem file to manager
* Bump python in CI instance
* Bump pip in CI container
* Remove pip sudo in CI container
* Fix launch script pip version equals
* Ini converted into strings
* Properly pass test_dir to opts in CI
* First pass at GH-A
* Round 2 CI fixes
* Try changes
* Remove CircleCI | Switch to fancy GH-A
* Rename self-host setup script
* Update chmod
* Use - instead of _ for env. vars
* Rename some defs | Remove extra imports
* Small comment updates
* Forgot to import in ini-api tests | Small comment on Fabric timeouts
* Add sys to linux poweroff
* Update linux timeout, fix small imports
* Update comment
* Fix-up workflow-monitor.py
* Avoid excessive logging in run-linux | Terminate spot instances after max-runtime
* Add more workflow-monitor states | Add pty=False to running workloads
* Update CI documentation | Add CI badge [ci skip]
* Don't use spot instances
* Update CI readme
* Determine runner version from remote repo and check for runner setup
* Address PR comments
* Update CI_README location of where to find IPs | Forgot ret_code
* Only run CI on prs/pushes to dev/main/master
* Fix terminate_workflow_instances in init-manager.py
* Cleanup FireSim repo cloning | Only run CI on PRs (since its runs on merge commit)
* Convert MMIO word addresses -> byte addresses
This makes address handling more uniform across the RTL and driver, leading to fewer points of confusion, and making it simpler to debug waveforms.
* Fix wide peeks and pokes
Nandor Licker