Commit Graph

3445 Commits

Author SHA1 Message Date
David Biancolin 5a1c4e727c [SBT] Don't push stuff on to midas's RT classpath
Invoke from the parent project instead
2020-06-21 19:52:12 +00:00
David Biancolin fda2ed3d04 [assert] Add a test that randomly generates an assert module hierarchy 2020-06-20 17:50:31 -07:00
David Biancolin 3dc12dcb91 [midasexamples] Factor log-diffing utils into more reusable form 2020-06-20 17:48:48 -07:00
David Biancolin 186412f8ed [assert] Fix bridge driver instantation when using 4+ clock domains 2020-06-20 17:47:45 -07:00
David Biancolin 7c7d3709b5 [assert] Fix a bug that would lead to double counting asserts in tests 2020-06-20 17:46:08 -07:00
David Biancolin 90dbfc27af
Merge pull request #579 from firesim/circleci-badge
Add CircleCI badge to README.md
2020-06-20 17:01:04 -07:00
David Biancolin 40b900c5ca [assert] Fix submodule ordering in concatenations 2020-06-20 02:00:17 -07:00
David Biancolin b816c3a24c Fix indexing bug in assertion synth introduced by multiclock 2020-06-17 02:46:12 -07:00
David Biancolin 133f787a81
Add CircleCI badge to README.md 2020-05-31 22:49:41 -07:00
David Biancolin c2d8e3a46e
Merge pull request #578 from firesim/1.10-release-prep
1.10 RC1
2020-05-31 14:29:40 -07:00
David Biancolin c01b43c76c Bump chipyard to 1.3.0 proto-release
[ci skip] This just updates the changelog
2020-05-31 21:23:17 +00:00
David Biancolin 01e169aa68 Update CHANGELOG [ci skip] 2020-05-31 21:15:21 +00:00
David Biancolin 82b5100c11 [docs] machine-launchstatus does not include output 2020-05-31 21:04:32 +00:00
David Biancolin 85013e4041 Remove FIRRTL API mappings until they can be done in an automated fashion 2020-05-31 20:28:46 +00:00
David Biancolin a9a7b69fd6 Bump CY again; should not change generated RTL 2020-05-31 20:25:42 +00:00
David Biancolin 183c405447 Bump aws-fpga-firesim to tagged release 2020-05-31 20:23:41 +00:00
David Biancolin 77afce9949 Merge remote-tracking branch 'origin/master' into 1.10-rc1 2020-05-31 19:22:02 +00:00
David Biancolin 08c5df941c Merge remote-tracking branch 'origin/dev' into 1.10-rc1 2020-05-31 19:20:10 +00:00
David Biancolin b9c52eafa3 Remove gemmini from default AGFIs 2020-05-31 19:18:32 +00:00
David Biancolin 02a135ccb9 Regenerate AGFIs 2020-05-31 19:16:10 +00:00
David Biancolin b1d12d15db Update workloads to use new hwdb names 2020-05-31 19:12:44 +00:00
David Biancolin be09cfe678
Merge pull request #577 from sifive/583_alias_WithoutTLMonitors
Alias RC WithoutTLMonitors into midas
2020-05-30 21:04:15 -07:00
Tim Snyder fbfb1e88c6 Alias RC WithoutTLMonitors into midas
Need to add it to my GoldenGate Config String (-ggcs) otherwise
I'm seeing TLMonitors added during SimulationMapping transform in GoldenGate

Additional detail at:
https://groups.google.com/forum/\#!topic/firesim/8loAr-29FbI
2020-05-30 18:05:03 -05:00
David Biancolin 4ef0a9e665
Merge pull request #576 from firesim/promote-submodule-partial-connects
Replace full instance Connects with PartialConnects in PromoteSubmodule
2020-05-29 19:31:55 -07:00
David Biancolin efe623bbdb Bump CY 2020-05-29 06:16:42 +00:00
Albert Magyar 801c5eefd0 Replace full instance Connects with PartialConnects in PromoteSubmodule 2020-05-29 04:07:00 +00:00
David Biancolin 4a2c7438be
Merge pull request #575 from firesim/mc-mem-opt
Port multi-port serialized mem optimization to multi-clock
2020-05-28 20:22:10 -07:00
David Biancolin cfb535f3a5
Merge pull request #574 from firesim/CI-ml-sim
Add most non-FireChip ScalaTests to CI
2020-05-28 20:21:29 -07:00
David Biancolin 5813cc96d6
[ci skip] Fix a comment typo
Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
2020-05-28 11:52:51 -07:00
Albert Magyar 2e635759f4 Port multi-port serialized mem optimization to multi-clock 2020-05-28 03:30:49 +00:00
David Biancolin 6d6073133f [make] [ci skip] Remove errant print 2020-05-28 02:09:34 +00:00
David Biancolin 0e28ad31bb Make dromajo archive recipe more portable 2020-05-28 01:13:53 +00:00
David Biancolin 9e50a7b055 [make] Disable all suffix rules to improve performance 2020-05-28 01:13:53 +00:00
David Biancolin d086d64096 Vastly speed up Make prerequisite resolution for midasexamples/fasedtests 2020-05-28 01:13:53 +00:00
David Biancolin 9aaf887f7d [CI] Add fasedtests, synth unittests, and firrtl tests to CI 2020-05-27 13:09:54 -07:00
David Biancolin 57fc979b35 [scalatests] Add Synthesixable tests to CI Suites 2020-05-26 23:53:44 -07:00
David Biancolin 6f58641c7c Vastly speed up Make prerequisite resolution for midasexamples/fasedtests 2020-05-26 23:53:38 -07:00
David Biancolin 6c54a1064c [midasexamples] Organize scalatests into two groups for CI 2020-05-26 22:08:53 -07:00
David Biancolin 133545a683 [SBT] Don't fork scala tesets for firesim subproject 2020-05-26 22:07:32 -07:00
David Biancolin 3143253dda
Merge pull request #573 from firesim/synth-unit-tests
Fix Synthesizable Unittests
2020-05-26 17:14:56 -07:00
David Biancolin 43d5f1eb90 Fix synthesizable unittest generation 2020-05-26 22:24:14 +00:00
David Biancolin 4528da6b96 [ml-sim] Pass top-level module through to Verilator correctly 2020-05-26 22:24:10 +00:00
David Biancolin 3462d970e0
Merge pull request #526 from firesim/trigger-docs
Trigger System Documentation
2020-05-25 21:31:18 -07:00
David Biancolin cbbb018c1a [docs] Update Trigger docs per Alon's comments. 2020-05-26 00:01:14 +00:00
David Biancolin 388fccadaa [midasexamples] Use the level sensitive enable in the TriggerWiring tests 2020-05-26 00:01:05 +00:00
David Biancolin 65ac551b18 [targetutils] placate Alon with a level sensitive enable 2020-05-25 16:41:45 -07:00
David Biancolin 7536cb152b [docs] First-pass Trigger system documentation 2020-05-25 16:41:45 -07:00
David Biancolin 1fd99896ed
Merge pull request #572 from firesim/scala-doc-ci-builds
CI-based Scaladoc Publishing
2020-05-25 15:30:35 -07:00
circle-ci-bot dd4240664a [CI] Add ci-skip to documentation commit messages 2020-05-25 13:55:22 -07:00
circle-ci-bot dd90215914 [CI] Don't publish scaladoc on feature branch 2020-05-25 12:25:23 -07:00