Port multi-port serialized mem optimization to multi-clock
This commit is contained in:
Albert Magyar
parent
3143253dda
commit
2e635759f4
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@ -6,11 +6,12 @@ import midas.widgets.{BridgeAnnotation, ClockBridgeAnnotation}
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import midas.passes.fame.{PromoteSubmodule, PromoteSubmoduleAnnotation, FAMEChannelConnectionAnnotation}
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import firrtl._
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import firrtl.annotations._
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import firrtl.ir._
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import firrtl.passes.{InferTypes, ResolveKinds}
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import firrtl.traversals.Foreachers._
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import firrtl.transforms.TopWiring.{TopWiringAnnotation, TopWiringTransform, TopWiringOutputFilesAnnotation}
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import firrtl.passes.wiring.{Wiring, WiringInfo}
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import firrtl.annotations._
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import Utils._
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import scala.collection.mutable
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@ -129,8 +130,13 @@ private[passes] class BridgeExtraction extends firrtl.Transform {
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// Annotate all bridge instances
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val instAnnoedState = annotateInstances(wrappedTopState)
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def normalize(state: CircuitState): CircuitState = {
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val cx = RemoveTrivialPartialConnects.run(InferTypes.run(ResolveKinds.run(state.circuit)))
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state.copy(circuit = cx)
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}
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// Promote all modules that are annotated as bridges
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val promotedState = promoteBridges(instAnnoedState)
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val promotedState = normalize(promoteBridges(instAnnoedState))
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// Propogate bridge annotations to the IO created on the true top module
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val commutedState = commuteBridgeAnnotations(promotedState)
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@ -0,0 +1,27 @@
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// See LICENSE for license details.
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package midas.passes
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import firrtl._
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import firrtl.ir._
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import firrtl.passes._
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import firrtl.Utils._
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import firrtl.Mappers._
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import firrtl.options.{Dependency, PreservesAll}
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object RemoveTrivialPartialConnects extends Pass with PreservesAll[Transform] {
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override def prerequisites =
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Dependency(InferTypes) +: Dependency(ResolveKinds) +: stage.Forms.WorkingIR
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private def onStmt(stmt: Statement): Statement = stmt match {
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case PartialConnect(i, l, e) if (l.tpe == e.tpe) => Connect(i, l, e)
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case s => s.map(onStmt)
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}
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private def onModule(m: DefModule): DefModule = m.map(onStmt)
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def run(c: Circuit): Circuit = {
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c.map(onModule)
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}
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}
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@ -17,7 +17,6 @@ import firrtl.Mappers._
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import firrtl.passes.LowerTypes.loweredName
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import firrtl.Utils.{BoolType, splitRef, mergeRef, create_exps, flow, module_type}
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import firrtl.passes.wiring._
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import fame.{FAMEChannelConnectionAnnotation, FAMEChannelPortsAnnotation, FAMEChannelAnalysis, FAME1Transform}
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import Utils._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy.LazyModule
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@ -117,7 +116,7 @@ private[passes] class SimulationMapping(targetName: String) extends firrtl.Trans
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Map(CircuitName(innerCircuit.main) -> Seq(CircuitName(outerCircuit.main))))
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val innerAnnos = loweredInnerState.annotations.filter(_ match {
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case _: FAMEChannelConnectionAnnotation | _: FAMEChannelPortsAnnotation => false
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case _: midas.targetutils.FAMEAnnotation => false
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case _: BridgeIOAnnotation => false
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case _ => true
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})
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@ -185,15 +185,15 @@ class RAMModelInst(name: String, val readPorts: Seq[ReadPort], val writePorts: S
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) ++ readConnects ++ writeConnects
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}
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def elaborateModel(parentCircuitNS: Namespace): (DefModule, Seq[Annotation]) = {
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def elaborateModel(parentCircuitNS: Namespace): Module = {
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val c3circuit = chisel3.Driver.elaborate(() =>
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new midas.models.sram.AsyncMemChiselModel(depth.toInt, dataWidth, readPorts.size, writePorts.size))
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val chirrtl = Parser.parse(chisel3.Driver.emit(c3circuit))
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val annos = PreLinkRenamingAnnotation(parentCircuitNS) +: c3circuit.annotations.map(_.toFirrtl)
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val state = new MiddleFirrtlCompiler().compile(CircuitState(chirrtl, ChirrtlForm, annos), Seq(PreLinkRenaming))
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require(state.circuit.modules.size == 1)
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val mod = state.circuit.modules.head
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(mod, state.annotations)
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val state = new MiddleFirrtlCompiler().compile(CircuitState(chirrtl, ChirrtlForm, Nil), Nil)
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require(state.circuit.modules.length == 1)
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state.circuit.modules.collectFirst({
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case m: Module => m.copy(name = name)
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}).get
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}
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}
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@ -225,21 +225,13 @@ class EmitAndWrapRAMModels extends Transform {
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val readWritePorts = annos.collect({ case anno: ModelReadWritePort => new ReadWritePort(anno, mod.ports)})
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require(readWritePorts.isEmpty)
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val (hostClock, updatedPortList) = mod.ports.find(p => p.tpe == ClockType && p.name == "clock") match {
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case Some(port) => (port, mod.ports)
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case None =>
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val cPort = Port(NoInfo, "clock", Input, ClockType)
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(cPort, cPort +: mod.ports)
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}
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val hostReset = mod.ports.find(_.name == "hostReset").get
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val hostClock = mod.ports.find(_.name == WrapTop.hostClockName).get
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val hostReset = mod.ports.find(_.name == WrapTop.hostResetName).get
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val name = ns.newName("RamModel")
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val inst = new RAMModelInst(name, readPorts, writePorts)
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val (module, newAnnos) = inst.elaborateModel(Namespace(c))
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addedModules += module
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addedAnnotations ++= newAnnos
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Module(NoInfo, mod.name, updatedPortList, Block(inst.emitStatements(WRef(hostClock), WRef(hostReset))))
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addedModules += inst.elaborateModel(Namespace(c))
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Module(NoInfo, mod.name, mod.ports, Block(inst.emitStatements(WRef(hostClock), WRef(hostReset))))
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}
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def onModule(mod: DefModule): DefModule = mod match {
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@ -249,11 +241,6 @@ class EmitAndWrapRAMModels extends Transform {
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val newCircuit = state.circuit.map(onModule)
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val renames = RenameMap.create(addedModules.map(m =>
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ModuleTarget(m.name, m.name) -> Seq(CircuitTarget(c.main))).toMap)
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state.copy(circuit = newCircuit.copy(modules = newCircuit.modules ++ addedModules),
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annotations = state.annotations ++ addedAnnotations,
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renames = Some(renames))
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state.copy(circuit = newCircuit.copy(modules = newCircuit.modules ++ addedModules))
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}
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}
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@ -5,14 +5,15 @@ package midas.passes.fame
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import java.io.{PrintWriter, File}
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import firrtl._
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import ir._
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import Mappers._
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import Utils._
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import firrtl.ir._
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import firrtl.Utils._
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import firrtl.passes.MemPortUtils
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import firrtl.analyses.InstanceGraph
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import annotations.{InstanceTarget, Annotation, SingleTargetAnnotation}
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import midas.targetutils.FirrtlFAMEModelAnnotation
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import scala.annotation.tailrec
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import scala.collection.mutable
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import mutable.{LinkedHashSet, LinkedHashMap}
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@ -20,15 +21,20 @@ class ExtractModel extends Transform {
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def inputForm = HighForm
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def outputForm = HighForm
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def promoteModels(state: CircuitState): CircuitState = {
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val anns = state.annotations.flatMap {
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case a @ FirrtlFAMEModelAnnotation(it) if (it.module != it.circuit) => Seq(a, PromoteSubmoduleAnnotation(it))
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case a => Seq(a)
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}
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if (anns.toSeq == state.annotations.toSeq) {
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state
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} else {
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promoteModels((new PromoteSubmodule).runTransform(state.copy(annotations = anns)))
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@tailrec
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private def promoteModels(state: CircuitState): CircuitState = {
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val fmAnns = state.annotations.collect({
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case ann: FirrtlFAMEModelAnnotation => ann.target.module -> ann
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}).toMap
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// Pick by order of parent in linearization -- don't pick children of main
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val modOrder = (new InstanceGraph(state.circuit)).moduleOrder.filterNot(_.name == state.circuit.main)
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val topModelAnn = modOrder.collectFirst(Function.unlift(dm => fmAnns.get(dm.name)))
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topModelAnn match {
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case None => state
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case Some(FirrtlFAMEModelAnnotation(it)) =>
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val anns = PromoteSubmoduleAnnotation(it) +: state.annotations
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val nextPromoted = (new PromoteSubmodule).runTransform(state.copy(annotations = anns))
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promoteModels(nextPromoted)
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}
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}
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@ -307,9 +307,14 @@ class FAMETransform extends Transform {
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renames
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}
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def staleTopPort(p: Port, analysis: FAMEChannelAnalysis): Boolean = p match {
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case Port(_, name, _, ClockType) => name != WrapTop.hostClockName
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case Port(_, name, _, _) => analysis.staleTopPorts.contains(analysis.topTarget.ref(name))
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}
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def transformTop(top: DefModule, analysis: FAMEChannelAnalysis): Module = top match {
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case Module(info, name, ports, body) =>
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val transformedPorts = ports.filterNot(p => analysis.staleTopPorts.contains(analysis.topTarget.ref(p.name))) ++
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val transformedPorts = ports.filterNot(p => staleTopPort(p, analysis)) ++
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analysis.transformedSinks.map(c => Port(NoInfo, s"${c}_sink", Input, analysis.getSinkHostDecoupledChannelType(c))) ++
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analysis.transformedSources.map(c => Port(NoInfo, s"${c}_source", Output, analysis.getSourceHostDecoupledChannelType(c)))
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val transformedStmts = Seq(body.map(updateNonChannelConnects(analysis))) ++
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@ -16,10 +16,18 @@ class LabelSRAMModels extends Transform {
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val confwriter = new passes.memlib.ConfWriter("NONE")
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val memutil = new passes.memlib.ReplaceMemMacros(confwriter)
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// Wrapper gets converted to strip clocks from ports, has one top-level clock
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def mem2Module(mem: DefMemory): Module = {
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val ports = passes.MemPortUtils.memType(mem).fields.map(f => Port(NoInfo, f.name, Input, f.tpe))
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val connects = ports.map(p => Connect(NoInfo, WSubField(WRef(mem.name), p.name), WRef(p.name)))
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Module(mem.info, mem.name, ports, Block(mem +: connects))
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val clockPort = Port(NoInfo, "clk", Input, ClockType)
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def stripClocks(tpe: Type): Type = tpe match {
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case BundleType(fields) => BundleType(fields.filterNot(_.tpe == ClockType))
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}
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val ports = mem.readers ++ mem.writers ++ mem.readwriters
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val connects = ports.map(p => PartialConnect(NoInfo, WSubField(WRef(mem.name), p), WRef(p)))
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val clkConnects = ports.map(p => Connect(NoInfo, WSubField(WSubField(WRef(mem.name), p), "clk"), WRef(clockPort)))
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val modPorts = clockPort +: passes.MemPortUtils.memType(mem).fields.map(f => Port(NoInfo, f.name, Input, stripClocks(f.tpe)))
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Module(mem.info, mem.name, modPorts, Block(mem +: connects ++: clkConnects))
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}
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override def execute(state: CircuitState): CircuitState = {
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@ -46,6 +54,11 @@ class LabelSRAMModels extends Transform {
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memModelAnnotations ++= mem.writers.map(rp => ModelWritePort(wrapperTarget.ref(rp)))
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memModelAnnotations ++= mem.readwriters.map(rp => ModelReadWritePort(wrapperTarget.ref(rp)))
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WDefInstance(mem.info, mem.name, wrapper.name, UnknownType)
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case c: Connect if (Utils.kind(c.loc) == MemKind && c.loc.tpe == ClockType) =>
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// change clock connects to target single mem wrapper clock
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val (wr, e) = Utils.splitRef(c.loc)
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val wrapperClock = Utils.mergeRef(wr, Utils.splitRef(e)._2)
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if (annotatedMems.contains(mt.ref(wr.name))) c.copy(loc = wrapperClock) else c
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case s => s
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}
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m.copy(body = m.body.map(onStmt))
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@ -70,11 +70,12 @@ class PromoteSubmodule extends Transform {
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}
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private def transformParentInstances(stmt: Statement, parentTemplate: WDefInstance, childTemplate: WDefInstance, namespace: Namespace, promotedNames: mutable.ArrayBuffer[String]): Statement = stmt match {
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// TODO: this does not handle instances inside of whens
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case oldParentInstance @ WDefInstance(_, _, parentTemplate.module, _) =>
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val retypedParentInst = oldParentInstance.copy(tpe = parentTemplate.tpe)
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val childPeerInst = childTemplate.copy(name = namespace.newName(oldParentInstance.name + "_" + childTemplate.name))
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promotedNames += childPeerInst.name
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val connection = Connect(childTemplate.info, instanceField(retypedParentInst, childTemplate.name), instanceRef(childPeerInst))
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val connection = PartialConnect(childTemplate.info, instanceField(retypedParentInst, childTemplate.name), instanceRef(childPeerInst))
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Block(Seq(retypedParentInst, childPeerInst, connection))
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case Block(stmts) => Block(stmts map (s => transformParentInstances(s, parentTemplate, childTemplate, namespace, promotedNames)))
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case s => s
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@ -95,7 +96,7 @@ class PromoteSubmodule extends Transform {
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val parentModule = updatedModules(parentInstances.head.module)
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val originalTarget = CircuitTarget(state.circuit.main).module(parentModule.name).instOf(childInstance.name, childInstance.module)
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if (parentModule.name == state.circuit.main) {
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throw new PassException("Cannot promote child instance ${childInstance.name} from top module ${parentModule.name}")
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throw new PassException(s"Cannot promote child instance ${childInstance.name} from top module ${parentModule.name}")
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}
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updatedModules(parentModule.name) = instanceToPort(parentModule, childInstance, childModule)
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val grandparentInstances = parentInstances.flatMap(reversedIGraph.getEdges(_))
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@ -65,6 +65,10 @@ object Or extends BinaryBooleanOp {
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val op = PrimOps.Or
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}
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object Xor extends BinaryBooleanOp {
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val op = PrimOps.Xor
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}
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object Neq extends BinaryBooleanOp {
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val op = PrimOps.Neq
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}
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@ -75,4 +79,12 @@ object Neq extends BinaryBooleanOp {
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object RegZeroPreset {
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def apply(info: Info, name: String, tpe: Type, clock: Expression): DefRegister =
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DefRegister(info, name, tpe, clock, zero, WRef(name))
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def apply(info: Info, name: String, clock: Expression): DefRegister =
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DefRegister(info, name, BoolType, clock, zero, WRef(name))
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}
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object ConditionalConnect {
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def apply(cond: Expression, lhs: Expression, rhs: Expression): Conditionally = {
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Conditionally(NoInfo, cond, Connect(NoInfo, lhs, rhs), EmptyStmt)
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}
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}
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