[ml-sim] Pass top-level module through to Verilator correctly

2020-05-26 08:05:16 +00:00 · 2020-05-26 08:05:16 +00:00 · 4528da6b96
parent 3462d970e0
commit 4528da6b96
1 changed files with 1 additions and 1 deletions
--- a/sim/midas/src/main/cc/rtlsim/Makefrag-verilator
+++ b/sim/midas/src/main/cc/rtlsim/Makefrag-verilator
@ -24,7 +24,7 @@ verilator_cc := $(emul_cc) $(verilator_harness)
 TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 >= 4.034) { print "--timescale 1ns/1ps"; }')
 override VERILATOR_FLAGS := \
 	$(TIMESCALE_OPTS) \
-	--top-module verilator_top \
+	--top-module $(top_module) \
 	-Wno-STMTDLY \
 	-O3 \
 	--output-split 10000 \