Commit Graph

109 Commits

Author SHA1 Message Date
Daniel Kroening 4b65ddedfa adder harness 2014-09-29 12:38:22 +00:00
Daniel Kroening 0f7924561d location -> source_location 2014-08-28 16:01:50 +00:00
Daniel Kroening 84024c4abf source_location 2014-08-27 16:11:26 +00:00
Daniel Kroening 09aa6ae8d1 locationt is now source_locationt 2014-08-27 15:48:12 +00:00
Daniel Kroening c373086133 arguments -> parameters 2014-08-13 21:52:16 +00:00
Daniel Kroening 143cec352b make test scripts work 2014-08-03 10:08:30 +00:00
Daniel Kroening 01ef99e80e print a banner 2014-06-30 08:33:52 +00:00
Daniel Kroening 1fb52a6857 verbosity is now in message_handler, not messaget 2014-06-29 20:50:43 +00:00
Daniel Kroening 630e6bfdf3 languaget has a new interface for messaging 2014-06-29 17:46:45 +00:00
Daniel Kroening 3b31563b10 fix exponentDifference 2014-04-08 19:19:28 +00:00
Daniel Kroening 3e02b5b402 cleanup 2014-04-08 16:22:55 +00:00
Daniel Kroening 6266f10ba0 fp_adder from Rajdeep 2014-04-08 16:21:44 +00:00
Daniel Kroening 67fecd7cef name collision 2014-04-07 16:37:37 +00:00
Daniel Kroening 6086ae8c2d fix harness conversion 2014-04-04 18:02:05 +00:00
Daniel Kroening 749d70e231 fix rounding mode passed to Verilog 2014-04-04 17:49:44 +00:00
Daniel Kroening c00c77467f further fixes 2014-04-03 09:45:44 +00:00
Daniel Kroening e723f7df2b fix pack routing 2014-04-02 22:40:34 +00:00
Daniel Kroening ba1a66b246 two fixes for unpacker (sign and exponent in the case of subnormal numbers) 2014-04-02 12:21:42 +00:00
Daniel Kroening 2b8ab2ec8b harness for unpacking 2014-04-02 12:20:59 +00:00
Daniel Kroening 38f26afaa9 use compareFloat 2014-03-29 12:23:34 +00:00
Daniel Kroening 75fde68962 another fix for module port types 2014-03-29 12:19:25 +00:00
Daniel Kroening 9057c3b446 fix for module port types 2014-03-29 12:13:45 +00:00
Daniel Kroening c90edda2ec added ID_output_register for Verilog 2014-03-29 12:00:10 +00:00
Daniel Kroening c94d35de15 mimimum width for left shifts 2014-03-29 10:47:11 +00:00
Daniel Kroening 2b4ba158ef avoid boolean shift expressions 2014-03-27 22:41:03 +00:00
Daniel Kroening 21a1b0f948 further fix for shifts 2014-03-27 13:34:31 +00:00
Daniel Kroening a4b23ec5ac fix for shifts 2014-03-26 22:05:44 +00:00
Daniel Kroening cbe846b62a test for module output registers 2014-03-26 21:47:15 +00:00
Daniel Kroening faf069e182 harness 2014-03-26 21:29:47 +00:00
Daniel Kroening 52e4d9b538 form 2014-03-26 21:17:09 +00:00
Daniel Kroening f5afc56ed9 fix for gen_interface 2014-03-26 20:49:11 +00:00
Daniel Kroening 3233b4d6b7 nudges for integer types 2014-03-26 20:29:58 +00:00
Daniel Kroening ef6f0adc85 Fix from Rajdeep 2014-03-26 20:07:30 +00:00
Daniel Kroening 598e55b7b9 more Verilog 2014-03-26 17:29:20 +00:00
Daniel Kroening 69152d5380 more Verilog 2014-03-26 14:55:26 +00:00
Daniel Kroening a16c401ec5 more Verilog 2014-03-26 14:28:11 +00:00
Daniel Kroening 157fff7db6 more Verilog 2014-03-26 13:57:49 +00:00
Daniel Kroening da473e9f05 more Verilog 2014-03-26 13:42:32 +00:00
Daniel Kroening 212ca2720b avoided some pointers 2014-03-26 13:26:30 +00:00
Daniel Kroening 7c39af0695 more Verilog 2014-03-26 13:14:08 +00:00
Daniel Kroening 95d01df125 more Verilog 2014-03-26 13:04:11 +00:00
Daniel Kroening b326fee47f more 2014-03-26 10:43:10 +00:00
Daniel Kroening 3fd3b2cd64 more Verilog 2014-03-26 10:41:15 +00:00
Daniel Kroening bd0d1e70a9 more 2014-03-26 10:37:39 +00:00
Daniel Kroening 3032df6418 clean normaliseUp 2014-03-26 10:33:35 +00:00
Daniel Kroening 084b0ba852 avoid tabs 2014-03-26 10:15:59 +00:00
Daniel Kroening 1c5e54c07b adder from Martin 2014-03-26 09:31:28 +00:00
Daniel Kroening 50b2ca9415 avoid atoi 2014-03-23 13:07:13 +00:00
Daniel Kroening 3e29f7551a fixed define 2014-03-18 20:17:04 +00:00
Daniel Kroening c983a95371 time is now typed 2014-01-07 15:25:49 +00:00