more Verilog
This commit is contained in:
Daniel Kroening
parent
bd0d1e70a9
commit
3fd3b2cd64
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@ -0,0 +1,601 @@
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`define RNE 0
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`define RNA 1
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`define RTP 2
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`define RTN 3
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`define RTZ 4
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// Normalises a denormal number or deal with catastrophic cancelation
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module normaliseUp(
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input [9:0] uf_exponent_in,
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input [23:0] uf_significand_in,
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output reg [9:0] uf_exponent,
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output reg [23:0] uf_significand);
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reg [5:0] shift;
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always @(*) begin
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shift = 0;
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uf_exponent = uf_exponent_in;
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uf_significand = uf_significand_in;
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`ifdef 0
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if ((0xFFFF00 & uf->significand) == 0) {
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uf->significand <<= 16;
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shift += 16;
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}
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if ((0xFF0000 & uf->significand) == 0) {
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uf->significand <<= 8;
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shift += 8;
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}
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if ((0xF00000 & uf->significand) == 0) {
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uf->significand <<= 4;
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shift += 4;
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}
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if ((0xC00000 & uf->significand) == 0) {
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uf->significand <<= 2;
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shift += 2;
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}
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if ((0x800000 & uf->significand) == 0) {
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uf->significand <<= 1;
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shift += 1;
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}
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uf_exponent -= shift;
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`endif
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end // always
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endmodule
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`define BIAS 127
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module unpack(
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input [31:0] f,
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output reg uf_nan, uf_inf, uf_zero, uf_subnormal, uf_sign,
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output reg [9:0] uf_exponent,
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output reg [23:0] uf_significand);
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wire sign;
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wire [7:0] exponent;
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wire [22:0] significand;
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// split up f
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assign { sign, exponent, significand } = f;
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always @(*) begin
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uf_sign = sign;
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if (exponent == 0) begin
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if (significand == 0) begin
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//makeZero(&uf);
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end
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else begin
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uf_nan = 0;
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uf_inf = 0;
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uf_zero = 0;
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uf_subnormal = 1;
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uf_exponent = -126;
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uf_significand = significand;
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//normaliseUp(&uf);
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end
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end
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else if (exponent == 'hff) begin
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if (significand == 0) begin
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//makeInf(&uf);
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end
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else begin
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//makeNaN(&uf);
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end
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end
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else begin
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// Normal
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uf_nan = 0;
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uf_inf = 0;
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uf_zero = 0;
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uf_subnormal = 0;
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uf_exponent = exponent - `BIAS;
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uf_significand = 'h800000 | significand;
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end
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end // always
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endmodule
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module pack(
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input uf_nan, uf_inf, uf_zero, uf_subnormal, uf_sign,
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input [9:0] uf_exponent,
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input [23:0] uf_significand,
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output [31:0] f);
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reg sign;
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reg [7:0] exponent;
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reg [22:0] significand;
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reg [8:0] biased;
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always @(*) begin
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sign = uf_sign;
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if (uf_nan) begin
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exponent = 'hff;
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significand = 'h40b2bd; // qNaN
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end
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else if (uf_inf) begin
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exponent = 'hff;
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significand = 'h0;
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end
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else if (uf_zero) begin
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exponent = 'h0;
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significand = 'h0;
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end
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else if (uf_subnormal) begin
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biased = uf_exponent+`BIAS-1;
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exponent = 'h0;
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significand = uf_significand >> -biased;
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end
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else begin
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exponent = uf_exponent + `BIAS;
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significand = 'h7fffff & uf_significand; // Remove leading 1
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end
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end // always
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// staple together
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assign f = 123; //sign o exponent o significand;
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endmodule
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// Perform the actual increment caused by rounding and correct the
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// exponent if needed.
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module roundInc(); //(unpackedFloat *result, uint64_t increment) {
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`ifdef 0
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uint32_t incremented = result->significand + increment;
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if (incremented == (1<<24)) {
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assert((incremented & 0x1) == 0x0);
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incremented >>= 1;
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++result->exponent;
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// Note that carrying into the exponent would be possible with
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// packed representations
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}
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assert(incremented < (1<<24));
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result->significand = incremented;
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`endif
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endmodule
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// Make the decision of whether to round or not.
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module rounder(); // (int roundingMode, unpackedFloat *result, uint8_t guardBit, uint8_t stickyBit) {
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`ifdef 0
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uint64_t increment = 1;
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if (result->exponent < -150) {
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// Even rounding up will not make this representable
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makeZero(result);
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return;
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} else if (result->exponent < -126) {
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// For subnormals, correct the guard and sticky bits
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int subnormalAmount = -(result->exponent + 126);
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increment = 1 << subnormalAmount;
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stickyBit = stickyBit | guardBit |
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((((1 << (subnormalAmount - 1)) - 1) & result->significand) ? 1 : 0);
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guardBit = ((1 << (subnormalAmount - 1)) & result->significand) ? 1 : 0;
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result->significand &= ~(increment - 1);
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}
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/* Round to fixed significand length */
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switch (roundingMode) {
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case RNE :
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if (guardBit) {
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if (stickyBit || (result->significand & increment)) {
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roundInc(result, increment);
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}
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}
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break;
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case RNA :
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if (guardBit) {
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roundInc(result, increment);
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}
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break;
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case RTP :
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if ((result->sign == 0) && (guardBit || stickyBit)) {
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roundInc(result, increment);
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}
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break;
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case RTN :
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if ((result->sign == 1) && (guardBit || stickyBit)) {
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roundInc(result, increment);
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}
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break;
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case RTZ :
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// No rounding needed
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break;
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}
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/* Round to fixed exponent length */
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switch (roundingMode) {
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case RNE :
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case RNA :
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if (result->exponent > 127) {
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makeInf(result);
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}
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break;
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case RTP :
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if (result->exponent > 127) {
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if (result->sign == 0) {
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makeInf(result);
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} else {
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makeMax(result);
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}
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}
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break;
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case RTN :
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if (result->exponent > 127) {
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if (result->sign == 1) {
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makeInf(result);
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} else {
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makeMax(result);
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}
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}
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break;
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case RTZ :
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if (result->exponent > 127) {
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makeMax(result);
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}
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break;
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}
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if (result->exponent < -126) {
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result->subnormal = 1;
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}
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`endif
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endmodule // rounder
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module dualPathAdder(); //int isAdd, int roundingMode, unpackedFloat *uf, unpackedFloat *ug, unpackedFloat *result) {
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`ifdef 0
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unpackedFloat larger;
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unpackedFloat smaller;
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uint8_t guardBit = 0;
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uint8_t stickyBit = 0;
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/* Flags -- result will be normal unless otherwise marked */
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result->nan = 0;
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result->inf = 0;
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result->zero = 0;
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result->subnormal = 0;
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initUnpackedFloat(&larger);
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initUnpackedFloat(&smaller);
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/* Compute the difference between exponents */
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int exponentDifference = uf->exponent - ug->exponent;
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/* Order by exponent */
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if ((exponentDifference > 0) ||
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((exponentDifference == 0) && (uf->significand > ug->significand))) {
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larger = *uf;
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smaller = *ug;
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result->sign = larger.sign;
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} else {
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larger = *ug;
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smaller = *uf;
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exponentDifference = -exponentDifference;
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result->sign = isAdd ? larger.sign : ~larger.sign;
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}
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result->exponent = larger.exponent;
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/* Work out if it is an effective subtract */
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/*
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if (larger.sign == 0) {
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negateResult = 0;
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effectiveSubtract = ~isAdd ^ smaller.sign;
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} else {
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negateResult = 1;
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effectiveSubtract = isAdd ^ smaller.sign
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}
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*/
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// Simplifies to ...
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int effectiveSubtract = larger.sign ^ (isAdd ? 0 : 1) ^ smaller.sign;
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// 'decimal point' after the 26th bit, LSB 2 bits are 0
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// 26 so that we can cancel one and still have 24 + guard bits
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uint32_t lsig = larger.significand << 2;
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uint32_t ssig = smaller.significand << 2;
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uint32_t sum = 0xFFFFFFFF;
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/* Split the two paths */
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if (exponentDifference <= 1) {
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/* Near path */
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// Align
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ssig >>= exponentDifference;
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if (effectiveSubtract) {
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/* May have catestrophic cancelation */
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uint32_t diff = lsig - ssig;
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assert((diff & 0xFC000000) == 0); // result is up to 26 bit
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if (diff == 0) { // Fully cancelled
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makeZero(result);
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/* IEEE-754 2008 says:
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* When the sum of two operands with opposite signs (or the
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* difference of two operands with like signs) is exactly
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* zero, the sign of that sum (or difference) shall be +0 in
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* all rounding-direction attributes except
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* roundTowardNegative; under that attribute, the sign of an
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* exact zero sum (or difference) shall be −0. However, x + x
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* = x − (−x) retains the same sign as x even when x is zero.
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*/
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result->sign = (roundingMode == RTN) ? 1 : 0;
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return; // No need to round
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} else if (diff & 0x02000000) { // 26 bit result
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sum = diff << 1;
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// Sticky bits are 0
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assert((sum & 0x3) == 0);
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goto extract;
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} else { // Some cancelation
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--result->exponent;
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result->significand = diff >> 1;
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guardBit = 0;
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stickyBit = 0;
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normaliseUp(result);
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// Won't underflow due to an exciting property of subnormal
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// numbers. Also, clearly, won't overflow. Furthermore,
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// won't increment. Thus don't need to call the rounder -- as
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// long as the subnormal flag is correctly set.
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// goto rounder;
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result->subnormal = (result->exponent < -126) ? 1 : 0;
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return;
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}
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} else {
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// Near addition is the same as far addition
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// except without the need to align first.
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// Thus fall through...
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}
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} else {
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/* Far path */
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if (exponentDifference > 26) {
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result->significand = larger.significand;
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result->subnormal = larger.subnormal;
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return;
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} else {
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if (effectiveSubtract) {
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ssig = (~ssig) + 1;
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}
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// Align
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int i;
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for (i = 1; i <= 26; i <<= 1) {
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if (exponentDifference & i) {
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uint32_t iOnes = ((1<<i) - 1);
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stickyBit |= ((ssig & iOnes) ? 1 : 0);
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// Sign extending shift
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if (effectiveSubtract) {
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ssig = (ssig >> i) | (iOnes << (32 - i));
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} else {
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ssig = (ssig >> i);
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}
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}
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}
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}
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}
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// Decimal point is after 26th bit
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sum = lsig + ssig;
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if (effectiveSubtract) {
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// Due to exponent difference, sum is either 25 or 26 bit
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assert((0xFC000000ul & sum) == 0x0);
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assert((0x03000000ul & sum) != 0x0);
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if (sum & 0x02000000ul) { // 26 bit
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sum <<= 1;
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} else { // 25 bit
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--result->exponent;
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sum <<= 2;
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}
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// Decimal point is now after the 27th bit
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} else {
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// sum is either 26 or 27 bits
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assert((0xF8000000ul & sum) == 0x0);
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assert((0x06000000ul & sum) != 0x0);
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if (sum & 0x04000000ul) { // 27 bit
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++result->exponent;
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} else { // 26 bit
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sum <<= 1;
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}
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}
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extract:
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// Decimal point is now after the 27th bit
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result->significand = sum >> 3;
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guardBit = (sum >> 2) & 0x1;
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stickyBit |= (((sum >> 1) & 0x1) | (sum & 0x1));
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// Can be simplified as the subnormal case implies no rounding
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rounder :
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rounder(roundingMode, result, guardBit, stickyBit);
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`endif
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endmodule // dualPathAdder
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module fp_add_sub(
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input isAdd,
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input [2:0] roundingMode,
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input [31:0] f,
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input [31:0] g,
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output [31:0] result);
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// unpack f
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wire uf_nan, uf_inf, uf_zero, uf_subnormal, uf_sign;
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wire [9:0] uf_exponent;
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wire [23:0] uf_significand;
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unpack unpack_f(f, uf_nan, uf_inf, uf_zero, uf_subnormal, uf_sign, uf_exponent, uf_significand);
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// unpack g
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wire ug_nan, ug_inf, ug_zero, ug_subnormal, ug_sign;
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wire [9:0] ug_exponent;
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wire [23:0] ug_significand;
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unpack unpack_g(g, ug_nan, ug_inf, ug_zero, ug_subnormal, ug_sign, ug_exponent, ug_significand);
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// set up unpacked result
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reg result_nan, result_inf, result_zero, result_subnormal, result_sign;
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reg [9:0] result_exponent;
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reg [23:0] result_significand;
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always @(*) begin
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// Handle all the special cases
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if (uf_nan || ug_nan) begin
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result_nan = 1;
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result_inf = 0;
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result_zero = 0;
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result_subnormal = 0;
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result_exponent = 'hff;
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result_significand = 0;
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end
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else if (uf_inf) begin
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`ifdef 0
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if ((ug->inf) &&
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((isAdd) ? uf->sign != ug->sign : uf->sign == ug->sign)) {
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makeNaN(result);
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return;
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} else {
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makeInf(result);
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result->sign = uf->sign;
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return;
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}
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`endif
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end
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else if (ug_inf) begin
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//makeInf(result);
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//result->sign = (isAdd) ? ug->sign : ~ug->sign;
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end
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else if (uf_zero) begin
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if (ug_zero) begin
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`ifdef 0
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makeZero(result);
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unsigned int flip = (isAdd) ? 0 : 1;
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if (roundingMode == RTN) {
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result->sign = uf->sign & (flip ^ ug->sign);
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} else {
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result->sign = uf->sign | (flip ^ ug->sign);
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|
||||
}
|
||||
return;
|
||||
`endif
|
||||
end
|
||||
|
||||
else begin // ug_zero
|
||||
//*result = *ug;
|
||||
//result->sign = (isAdd) ? result->sign : ~result->sign;
|
||||
end
|
||||
end
|
||||
|
||||
else if (ug_zero) begin
|
||||
//*result = *uf;
|
||||
end
|
||||
|
||||
else begin
|
||||
//dualPathAdder(isAdd,roundingMode,uf,ug,result);
|
||||
end
|
||||
|
||||
end // always
|
||||
|
||||
// now pack the result
|
||||
|
||||
pack pack_result(result_nan, result_inf, result_zero, result_subnormal,
|
||||
result_sign, result_exponent, result_significand, result);
|
||||
|
||||
endmodule
|
||||
|
||||
`ifdef 0
|
||||
float sub(int roundingMode, float f, float g) {
|
||||
unpackedFloat uf = unpack(f);
|
||||
unpackedFloat ug = unpack(g);
|
||||
unpackedFloat result;
|
||||
|
||||
initUnpackedFloat(&result);
|
||||
|
||||
addUnit(0,roundingMode,&uf,&ug,&result);
|
||||
//check(result);
|
||||
|
||||
float res = pack(result);
|
||||
|
||||
return res;
|
||||
}
|
||||
`endif
|
||||
Loading…
Reference in New Issue