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Sequential Logic

Registers

Retain state until updated:

reg = Reg(U.w(32))
counter = RegInit(U.w(32)(0))

RAM/ROM/Mem

class MemDemo(Module):
    io = IO(
        i=Input(U.w(8)),
        o=Output(U.w(8)),
    )

    m = Mem(10, U.w(8))
    m[U(2)] @= io.i
    io.o @= m[U(2)]