mirror of https://github.com/llvm/circt.git
79 lines
4.6 KiB
MLIR
79 lines
4.6 KiB
MLIR
// RUN: circt-opt -lower-firrtl-to-hw -verify-diagnostics -split-input-file -mlir-disable-threading %s
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// module MemAggregate :
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// input clock1 : Clock
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// input clock2 : Clock
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//
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// mem _M : @[Decoupled.scala 209:24]
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// data-type => { id : UInt<4>, other: SInt<8> }
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// depth => 20
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// read-latency => 0
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// write-latency => 1
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// reader => read
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// writer => write
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// read-under-write => undefined
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// COM: This is a memory with aggregates which is currently not supported.
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firrtl.circuit "Div" {
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firrtl.module @Div(in %clock1: !firrtl.clock, in %clock2: !firrtl.clock) {
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// expected-error @+2 {{'firrtl.mem' op should have already been lowered from a ground type to an aggregate type using the LowerTypes pass}}
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// expected-error @+1 {{'firrtl.mem' op LowerToHW couldn't handle this operation}}
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%_M_read, %_M_write = firrtl.mem Undefined {depth = 20 : i64, name = "_M", portNames = ["read", "write"], readLatency = 0 : i32, writeLatency = 1 : i32} : !firrtl.bundle<addr: uint<5>, en: uint<1>, clk: clock, data flip: bundle<id: uint<4>, other: sint<8>>>, !firrtl.bundle<addr: uint<5>, en: uint<1>, clk: clock, data: bundle<id: uint<4>, other: sint<8>>, mask: bundle<id: uint<1>, other: uint<1>>>
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}
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}
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// -----
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// module MemOne :
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// mem _M : @[Decoupled.scala 209:24]
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// data-type => { id : UInt<4>, other: SInt<8> }
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// depth => 1
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// read-latency => 0
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// write-latency => 1
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// reader => read
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// writer => write
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// read-under-write => undefined
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// COM: This is an aggregate memory which is not supported.
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firrtl.circuit "MemOne" {
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firrtl.module @MemOne() {
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// expected-error @+2 {{'firrtl.mem' op should have already been lowered from a ground type to an aggregate type using the LowerTypes pass}}
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// expected-error @+1 {{'firrtl.mem' op LowerToHW couldn't handle this operation}}
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%_M_read, %_M_write = firrtl.mem Undefined {depth = 1 : i64, name = "_M", portNames=["read", "write"], readLatency = 0 : i32, writeLatency = 1 : i32} : !firrtl.bundle<addr: uint<1>, en: uint<1>, clk: clock, data flip: bundle<id: uint<4>, other: sint<8>>>, !firrtl.bundle<addr: uint<1>, en: uint<1>, clk: clock, data: bundle<id: uint<4>, other: sint<8>>, mask: bundle<id: uint<1>, other: uint<1>>>
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}
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}
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// -----
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// COM: Unknown widths are unsupported
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firrtl.circuit "UnknownWidth" {
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// expected-error @+1 {{cannot lower this port type to HW}}
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firrtl.module @UnknownWidth(in %a: !firrtl.uint) {}
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}
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// -----
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// This should not produce an error.
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// https://github.com/llvm/circt/issues/778
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firrtl.circuit "zero_width_mem" {
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firrtl.module @zero_width_mem(in %clock: !firrtl.clock, in %reset: !firrtl.uint<1>, in %r0en: !firrtl.uint<1>) {
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%c0_ui4 = firrtl.constant 0 : !firrtl.uint<4>
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%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
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%c0_ui25 = firrtl.constant 0 : !firrtl.uint<25>
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%tmp41_r0, %tmp41_w0 = firrtl.mem Undefined {depth = 10 : i64, name = "tmp41", portNames = ["r0", "w0"], readLatency = 0 : i32, writeLatency = 1 : i32} : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: uint<0>>, !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: uint<0>, mask: uint<1>>
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%0 = firrtl.subfield %tmp41_r0[clk] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: uint<0>>
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firrtl.connect %0, %clock : !firrtl.clock, !firrtl.clock
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%1 = firrtl.subfield %tmp41_r0[en] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: uint<0>>
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firrtl.connect %1, %r0en : !firrtl.uint<1>, !firrtl.uint<1>
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%2 = firrtl.subfield %tmp41_r0[addr] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: uint<0>>
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firrtl.connect %2, %c0_ui4 : !firrtl.uint<4>, !firrtl.uint<4>
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%3 = firrtl.subfield %tmp41_w0[clk] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: uint<0>, mask: uint<1>>
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firrtl.connect %3, %clock : !firrtl.clock, !firrtl.clock
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%4 = firrtl.subfield %tmp41_w0[en] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: uint<0>, mask: uint<1>>
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firrtl.connect %4, %r0en : !firrtl.uint<1>, !firrtl.uint<1>
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%5 = firrtl.subfield %tmp41_w0[addr] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: uint<0>, mask: uint<1>>
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firrtl.connect %5, %c0_ui4 : !firrtl.uint<4>, !firrtl.uint<4>
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%6 = firrtl.subfield %tmp41_w0[mask] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: uint<0>, mask: uint<1>>
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firrtl.connect %6, %c0_ui1 : !firrtl.uint<1>, !firrtl.uint<1>
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%7 = firrtl.subfield %tmp41_w0[data] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: uint<0>, mask: uint<1>>
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}
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}
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