Andrew Lenharth 643571890f [FIRRTL] Error when seeing inner symbols on zero-width wires and nodes in LowerToHW ... Closes #5590 and #7252		2024-07-01 10:40:44 -05:00
..
emit-chisel-asserts-as-sva.mlir	[LowerToHW] Emission Option for verification flavors (#6885)	2024-04-02 14:09:38 +09:00
errors.mlir	[FIRRTL] Update subfield format (#4430)	2022-12-10 06:54:57 -08:00
intrinsics-errors.mlir	[NFC, FIRRTL] Rename StrictConnect to MatchingConnect. (#7116)	2024-06-04 09:19:00 -05:00
intrinsics.mlir	[FIRRTL][Verif][LTL] Replace `ltl.disable` with an enable folded into `verif.assert` (#7150)	2024-06-20 11:24:37 -07:00
lower-to-hw-errors.mlir	[FIRRTL] Error when seeing inner symbols on zero-width wires and nodes in LowerToHW	2024-07-01 10:40:44 -05:00
lower-to-hw-memories.mlir	[NFC, FIRRTL] Rename StrictConnect to MatchingConnect. (#7116)	2024-06-04 09:19:00 -05:00
lower-to-hw-module.mlir	[SV] Use a symbol in macro identifiers (#6777)	2024-03-04 13:12:27 +02:00
lower-to-hw.mlir	[NFC, FIRRTL] Rename StrictConnect to MatchingConnect. (#7116)	2024-06-04 09:19:00 -05:00
module-hierarchy-file.mlir	[NFC] test/*: Add newline to files missing EOF newline.	2023-07-07 15:30:10 -05:00
zero-width.mlir	[FIRRTL] Change min width of shr for UInt to 0 (#6698)	2024-02-15 14:17:02 -08:00