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circt/test/Conversion
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cepheus acb558822f
[Moore] SymbolVisibility attribute support for SVModuleOp (#7278) 
We can append the appropriate symbol visibility to svmoduleOp according
to the structures of instanceSymbol provided by the slang front-end. slang
provides a function to get the root of the design. Calling this method
could get all top-level instanceSymbols and help determine which ones
should be tagged. Note that the visibility attribute now used does not
contain the `nested`.
 		2024-07-09 12:03:18 +08:00
..
AffineToLoopSchedule [LoopSchedule] Move PipelineWhile and Related Ops from Pipeline to LoopSchedule (#4947) 2023-04-18 11:56:07 -04:00
ArcToLLVM [Arc] Add support for struct and array states (#6508) 2023-12-11 14:22:25 -08:00
CFToHandshake [Handshake] `StandardToHandshake` -> `CFToHandshake` (#5938) 2023-08-25 09:24:26 +02:00
CalyxToFSM [Seq] Switch all seq ops to use seq.clock (#6139) 2023-09-18 16:38:32 +03:00
CalyxToHW Add emission for calyx std_signext (#6285) 2023-10-12 12:17:44 -04:00
CombToArith [CombToArith] Fix coarsening of division by zero UB (#6945) 2024-05-06 15:59:36 +02:00
CombToSMT [CombToSMT] Register dependency on func (#7098) 2024-05-28 21:46:54 +02:00
ConvertToArcs [Arc] StateOp: latency instead of lat in assembly format (#6562) 2024-01-12 07:54:39 +01:00
DCToHW [DC] Add merge lowering (#6943) 2024-05-07 10:21:25 +02:00
ExportChiselInterface [ExportChiselInterface] Support probe types (#5497) 2023-06-30 09:22:46 -06:00
ExportVerilog [FIRRTL][Verif][LTL] Replace `ltl.disable` with an enable folded into `verif.assert` (#7150) 2024-06-20 11:24:37 -07:00
FIRRTLToHW [FIRRTL] Error when seeing inner symbols on zero-width wires and nodes in LowerToHW 2024-07-01 10:40:44 -05:00
FSMToSV [FSM][Emit] Convert the FSMToSV pass to use `emit` ops (#6828) 2024-03-19 19:30:02 +02:00
HWArithToHW [HW] Change printer for modules (#6205) 2023-09-28 16:30:15 -05:00
HWToBTOR2 [FIRRTL][Verif][LTL] Replace `ltl.disable` with an enable folded into `verif.assert` (#7150) 2024-06-20 11:24:37 -07:00
HWToLLHD [HW] Change printer for modules (#6205) 2023-09-28 16:30:15 -05:00
HWToLLVM Bump LLVM (#7223) 2024-06-26 13:19:37 -07:00
HWToSMT [circt-lec] Port to SMT dialect based compiler pipeline (#6908) 2024-04-21 08:06:39 +02:00
HWToSV [HW] Change printer for modules (#6205) 2023-09-28 16:30:15 -05:00
HWToSystemC [HW] Change printer for modules (#6205) 2023-09-28 16:30:15 -05:00
HandshakeToDC [Handshake] Add control_merge deconstruction pattern (#6934) 2024-05-07 11:08:04 +02:00
HandshakeToHW [Seq] Add optional power-on value to `compreg` ops (#6255) 2023-10-09 11:11:15 +02:00
ImportVerilog [Moore] SymbolVisibility attribute support for SVModuleOp (#7278) 2024-07-09 12:03:18 +08:00
LLHDToLLVM Bump LLVM (#7223) 2024-06-26 13:19:37 -07:00
LTLToCore [FIRRTL][Verif][LTL] Replace `ltl.disable` with an enable folded into `verif.assert` (#7150) 2024-06-20 11:24:37 -07:00
LoopScheduleToCalyx [SCF-To-Calyx] Fixes Bugs (#5573) 2023-07-13 18:25:05 -04:00
MooreToCore [MooreToCore] Fix parse error for parameter (#7253) 2024-07-02 09:23:04 +08:00
PipelineToHW [PipelineToHW] Add optional power-on values to control registers (#6269) 2023-10-10 11:10:16 +02:00
SCFToCalyx [Calyx] Switch sequential memories to be true single port memories (#6765) 2024-02-29 11:15:34 -05:00
SMTToZ3LLVM [SMT] Add quantifier support to LLVM lowering (#6973) 2024-05-02 10:09:14 +02:00
SeqToSV [SeqToSV] Fix the ordering of the memory/register random init fragments (#6883) 2024-04-01 18:56:45 +03:00
SimToSV [SimToSV] Fix DPICall lowering to use `replaceOp` (#7192) 2024-06-17 19:44:20 +09:00
VerifToSMT Bump LLVM (#7223) 2024-06-26 13:19:37 -07:00
VerifToSV [HW] Change printer for modules (#6205) 2023-09-28 16:30:15 -05:00