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Analysis
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[HW] Add top module inference to InstanceGraph (#3592)
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2022-07-26 09:11:28 +02:00 |
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CAPI
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[CMake] Reduce number of deps (#3569)
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2022-07-20 17:37:24 -07:00 |
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Conversion
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[Pipeline][NFC] Rename `pipeline.stage` -> `pipeline.while.stage` (#3758)
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2022-08-22 10:20:00 +02:00 |
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Dialect
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[Pipeline][NFC] Rename `pipeline.stage` -> `pipeline.while.stage` (#3758)
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2022-08-22 10:20:00 +02:00 |
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Scheduling
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LLVM bump (as we know it) (#3074)
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2022-05-09 14:30:14 -07:00 |
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Target/ExportSystemC
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[ExportSystemC] Add emission patterns for the remaining systemc ops and constant op (#3735)
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2022-08-18 11:42:38 +02:00 |
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Transforms
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[Transform] [FIRTOOL] Add an pass to strip file locators with "fir" suffix (#3122)
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2022-07-06 21:12:32 +09:00 |
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Unit
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[Moore] Add SystemVerilog types (#2699)
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2022-03-04 08:48:45 +01:00 |
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circt-opt
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[StaticLogic] Rename dialect to 'Pipeline' (#3648)
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2022-08-04 10:58:40 +02:00 |
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circt-reduce
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[circt-reduce] Invert test exit code requirement (#3591)
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2022-07-25 14:14:37 +02:00 |
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circt-translate
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[LLHD] remove the LLHD-specific Verilog printer.
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2021-12-08 14:01:45 -08:00 |
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firtool
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[FIRRTL] Extend register randomization to split up large registers. (#3748)
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2022-08-17 22:04:20 -06:00 |
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handshake-runner
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[CMake] Reduce number of deps (#3569)
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2022-07-20 17:37:24 -07:00 |
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lib
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[NFC] Added newlines to the end of files
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2022-03-28 18:58:23 +03:00 |
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llhd-sim
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circt-reduce,firtool,llhd-sim: cleanup --help output, put options in category (#2979)
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2022-05-03 16:02:57 -05:00 |
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CMakeLists.txt
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[CMake] Reduce number of deps (#3569)
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2022-07-20 17:37:24 -07:00 |
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lit.cfg.py
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[Scheduling] Set up infrastructure for using OR-Tools' solvers. (#2465)
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2022-01-18 10:55:15 +01:00 |
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lit.site.cfg.py.in
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[Scheduling] Set up infrastructure for using OR-Tools' solvers. (#2465)
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2022-01-18 10:55:15 +01:00 |
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