terapines
/
circt
mirror of https://github.com/llvm/circt.git
2
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

[Pipeline][NFC] Rename `pipeline.stage` -> `pipeline.while.stage` (#3758)

This commit is contained in:
Morten Borup Petersen 2022-08-22 10:20:00 +02:00 committed by GitHub
parent 55515450ff
commit 5fc5b1d372
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
8 changed files with 89 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/circt/Dialect/Pipeline/Pipeline.td
View File

@ -101,9 +101,9 @@ def PipelineWhileOp : Op<Pipeline_Dialect, "while", []> {
}];
}
def PipelineStageOp : Op<Pipeline_Dialect, "stage",
def PipelineWhileStageOp : Op<Pipeline_Dialect, "while.stage",
[HasParent<"PipelineWhileOp">]> {
let summary = "Pipeline dialect pipeline stage.";
let summary = "Pipeline dialect while pipeline stage.";
let description = [{
This operation has a single-block region which dictates the operations that
may occur concurrently.
@ -160,7 +160,7 @@ def PipelineStageOp : Op<Pipeline_Dialect, "stage",
}
def PipelineRegisterOp : Op<Pipeline_Dialect, "register",
[ParentOneOf<["PipelineWhileOp", "PipelineStageOp"]>, Terminator]> {
[ParentOneOf<["PipelineWhileOp", "PipelineWhileStageOp"]>, Terminator]> {
let summary = "Pipeline dialect pipeline register.";
let description = [{
The `pipeline.register` terminates a pipeline stage and

3
lib/Conversion/AffineToPipeline/AffineToPipeline.cpp
View File

@ -441,7 +441,8 @@ LogicalResult AffineToPipeline::createPipelinePipeline(
// Create the stage itself.
auto startTimeAttr = builder.getIntegerAttr(
builder.getIntegerType(64, /*isSigned=*/true), startTime);
auto stage = builder.create<PipelineStageOp>(stageTypes, startTimeAttr);
auto stage =
builder.create<PipelineWhileStageOp>(stageTypes, startTimeAttr);
auto &stageBlock = stage.getBodyBlock();
auto *stageTerminator = stageBlock.getTerminator();
builder.setInsertionPointToStart(&stageBlock);

8
lib/Conversion/PipelineToCalyx/PipelineToCalyx.cpp
View File

@ -223,7 +223,7 @@ class BuildOpGroups : public calyx::FuncOpPartialLoweringPattern {
[&](auto op) { return buildOp(rewriter, op).succeeded(); })
.template Case<FuncOp, pipeline::PipelineWhileOp,
pipeline::PipelineRegisterOp,
pipeline::PipelineStageOp>([&](auto) {
pipeline::PipelineWhileStageOp>([&](auto) {
/// Skip: these special cases will be handled separately.
return true;
})
@ -906,7 +906,7 @@ class BuildPipelineRegs : public calyx::FuncOpPartialLoweringPattern {
funcOp.walk([&](pipeline::PipelineRegisterOp op) {
// Condition registers are handled in BuildWhileGroups.
auto *parent = op->getParentOp();
auto stage = dyn_cast<pipeline::PipelineStageOp>(parent);
auto stage = dyn_cast<pipeline::PipelineWhileStageOp>(parent);
if (!stage)
return;
@ -966,7 +966,7 @@ class BuildPipelineGroups : public calyx::FuncOpPartialLoweringPattern {
PatternRewriter &rewriter) const override {
for (auto pipeline : funcOp.getOps<pipeline::PipelineWhileOp>())
for (auto stage :
pipeline.getStagesBlock().getOps<pipeline::PipelineStageOp>())
pipeline.getStagesBlock().getOps<pipeline::PipelineWhileStageOp>())
if (failed(buildStageGroups(pipeline, stage, rewriter)))
return failure();
@ -974,7 +974,7 @@ class BuildPipelineGroups : public calyx::FuncOpPartialLoweringPattern {
}
LogicalResult buildStageGroups(pipeline::PipelineWhileOp whileOp,
pipeline::PipelineStageOp stage,
pipeline::PipelineWhileStageOp stage,
PatternRewriter &rewriter) const {
// Collect pipeline registers for stage.
auto pipelineRegisters =

52
lib/Dialect/Pipeline/PipelineOps.cpp
View File

@ -162,15 +162,15 @@ LogicalResult PipelineWhileOp::verify() {
int64_t lastStartTime = -1;
for (Operation &inner : stagesBlock) {
// Verify the stages block contains only `pipeline.stage` and
// Verify the stages block contains only `pipeline.while.stage` and
// `pipeline.terminator` ops.
if (!isa<PipelineStageOp, PipelineTerminatorOp>(inner))
return emitOpError("stages may only contain 'pipeline.stage' or "
if (!isa<PipelineWhileStageOp, PipelineTerminatorOp>(inner))
return emitOpError("stages may only contain 'pipeline.while.stage' or "
"'pipeline.terminator' ops, found ")
<< inner;
// Verify the stage start times are monotonically increasing.
if (auto stage = dyn_cast<PipelineStageOp>(inner)) {
if (auto stage = dyn_cast<PipelineWhileStageOp>(inner)) {
if (lastStartTime == -1) {
lastStartTime = stage.start();
continue;
@ -218,18 +218,18 @@ void PipelineWhileOp::build(OpBuilder &builder, OperationState &state,
}
//===----------------------------------------------------------------------===//
// PipelineStageOp
// PipelineWhileStageOp
//===----------------------------------------------------------------------===//
LogicalResult PipelineStageOp::verify() {
LogicalResult PipelineWhileStageOp::verify() {
if (start() < 0)
return emitOpError("'start' must be non-negative");
return success();
}
void PipelineStageOp::build(OpBuilder &builder, OperationState &state,
TypeRange resultTypes, IntegerAttr start) {
void PipelineWhileStageOp::build(OpBuilder &builder, OperationState &state,
TypeRange resultTypes, IntegerAttr start) {
OpBuilder::InsertionGuard g(builder);
state.addTypes(resultTypes);
@ -241,12 +241,24 @@ void PipelineStageOp::build(OpBuilder &builder, OperationState &state,
builder.create<PipelineRegisterOp>(builder.getUnknownLoc(), ValueRange());
}
unsigned PipelineWhileStageOp::getStageNumber() {
unsigned number = 0;
auto *op = getOperation();
auto parent = op->getParentOfType<PipelineWhileOp>();
Operation *stage = &parent.getStagesBlock().front();
while (stage != op && stage->getNextNode()) {
++number;
stage = stage->getNextNode();
}
return number;
}
//===----------------------------------------------------------------------===//
// PipelineRegisterOp
//===----------------------------------------------------------------------===//
LogicalResult PipelineRegisterOp::verify() {
PipelineStageOp stage = (*this)->getParentOfType<PipelineStageOp>();
PipelineWhileStageOp stage = (*this)->getParentOfType<PipelineWhileStageOp>();
// If this doesn't terminate a stage, it is terminating the condition.
if (stage == nullptr)
@ -263,18 +275,6 @@ LogicalResult PipelineRegisterOp::verify() {
return success();
}
unsigned PipelineStageOp::getStageNumber() {
unsigned number = 0;
auto *op = getOperation();
auto parent = op->getParentOfType<PipelineWhileOp>();
Operation *stage = &parent.getStagesBlock().front();
while (stage != op && stage->getNextNode()) {
++number;
stage = stage->getNextNode();
}
return number;
}
//===----------------------------------------------------------------------===//
// PipelineTerminatorOp
//===----------------------------------------------------------------------===//
@ -293,8 +293,9 @@ LogicalResult PipelineTerminatorOp::verify() {
// Verify `iter_args` are defined by a pipeline stage.
for (auto iterArg : iterArgs)
if (iterArg.getDefiningOp<PipelineStageOp>() == nullptr)
return emitOpError("'iter_args' must be defined by a 'pipeline.stage'");
if (iterArg.getDefiningOp<PipelineWhileStageOp>() == nullptr)
return emitOpError(
"'iter_args' must be defined by a 'pipeline.while.stage'");
// Verify pipeline terminates with the same result types as the pipeline.
auto opResults = results();
@ -307,8 +308,9 @@ LogicalResult PipelineTerminatorOp::verify() {
// Verify `results` are defined by a pipeline stage.
for (auto result : opResults)
if (result.getDefiningOp<PipelineStageOp>() == nullptr)
return emitOpError("'results' must be defined by a 'pipeline.stage'");
if (result.getDefiningOp<PipelineWhileStageOp>() == nullptr)
return emitOpError(
"'results' must be defined by a 'pipeline.while.stage'");
return success();
}

8
test/Conversion/AffineToPipeline/loops.mlir
View File

@ -15,7 +15,7 @@ func.func @minimal(%arg0 : memref<10xindex>) {
// CHECK: pipeline.register %[[COND_RESULT]]
// First stage.
// CHECK: %[[STAGE0:.+]] = pipeline.stage
// CHECK: %[[STAGE0:.+]] = pipeline.while.stage
// CHECK: %[[ITER_INC:.+]] = arith.addi %[[ITER_ARG]], %[[STEP]]
// CHECK: pipeline.register %[[ITER_INC]]
@ -34,19 +34,19 @@ func.func @dot(%arg0: memref<64xi32>, %arg1: memref<64xi32>) -> i32 {
// Pipeline boilerplate checked above, just check the stages computations.
// First stage.
// CHECK: %[[STAGE0:.+]]:3 = pipeline.stage
// CHECK: %[[STAGE0:.+]]:3 = pipeline.while.stage
// CHECK-DAG: %[[STAGE0_0:.+]] = memref.load %arg0[%arg2]
// CHECK-DAG: %[[STAGE0_1:.+]] = memref.load %arg1[%arg2]
// CHECK-DAG: %[[STAGE0_2:.+]] = arith.addi %arg2, %c1
// CHECK: pipeline.register %[[STAGE0_0]], %[[STAGE0_1]], %[[STAGE0_2]]
// Second stage.
// CHECK: %[[STAGE1:.+]] = pipeline.stage
// CHECK: %[[STAGE1:.+]] = pipeline.while.stage
// CHECK-DAG: %[[STAGE1_0:.+]] = arith.muli %[[STAGE0]]#0, %[[STAGE0]]#1 : i32
// CHECK: pipeline.register %[[STAGE1_0]]
// Third stage.
// CHECK: %[[STAGE2:.+]] = pipeline.stage
// CHECK: %[[STAGE2:.+]] = pipeline.while.stage
// CHECK-DAG: %[[STAGE2_0:.+]] = arith.addi %arg3, %2
// CHECK: pipeline.register %[[STAGE2_0]]

12
test/Conversion/PipelineToCalyx/convert_pipeline.mlir
View File

@ -42,7 +42,7 @@ func.func @minimal() {
%0 = arith.cmpi ult, %arg0, %c10_i64 : i64
pipeline.register %0 : i1
} do {
%0 = pipeline.stage start = 0 {
%0 = pipeline.while.stage start = 0 {
%1 = arith.addi %arg0, %c1_i64 : i64
pipeline.register %1 : i64
} : i64
@ -167,17 +167,17 @@ func.func @dot(%arg0: memref<64xi32>, %arg1: memref<64xi32>) -> i32 {
%1 = arith.cmpi ult, %arg2, %c64 : index
pipeline.register %1 : i1
} do {
%1:3 = pipeline.stage start = 0 {
%1:3 = pipeline.while.stage start = 0 {
%4 = memref.load %arg0[%arg2] : memref<64xi32>
%5 = memref.load %arg1[%arg2] : memref<64xi32>
%6 = arith.addi %arg2, %c1 : index
pipeline.register %4, %5, %6 : i32, i32, index
} : i32, i32, index
%2 = pipeline.stage start = 1 {
%2 = pipeline.while.stage start = 1 {
%4 = arith.muli %1#0, %1#1 : i32
pipeline.register %4 : i32
} : i32
%3 = pipeline.stage start = 4 {
%3 = pipeline.while.stage start = 4 {
%4 = arith.addi %arg3, %2 : i32
pipeline.register %4 : i32
} : i32
@ -228,12 +228,12 @@ module {
%0 = arith.cmpi ult, %arg2, %c4 : index
pipeline.register %0 : i1
} do {
%0:2 = pipeline.stage start = 0 {
%0:2 = pipeline.while.stage start = 0 {
%1 = memref.load %arg0[%arg2] : memref<4xi32>
%2 = arith.addi %arg2, %c1 : index
pipeline.register %1, %2 : i32, index
} : i32, index
pipeline.stage start = 1 {
pipeline.while.stage start = 1 {
memref.store %0#0, %arg1[%arg2] : memref<4xi32>
memref.store %0#0, %arg1[%arg2] : memref<4xi32>
pipeline.register

40
test/Dialect/Pipeline/errors.mlir
View File

@ -10,7 +10,7 @@ func.func @combinational_condition() {
%2 = arith.cmpi ult, %1, %arg0 : i32
pipeline.register %2 : i1
} do {
pipeline.stage start = 0 {
pipeline.while.stage start = 0 {
pipeline.register
}
pipeline.terminator iter_args(), results() : () -> ()
@ -26,7 +26,7 @@ func.func @single_condition() {
pipeline.while II = 1 iter_args(%arg0 = %false) : (i1) -> () {
pipeline.register %arg0, %arg0 : i1, i1
} do {
pipeline.stage start = 0 {
pipeline.while.stage start = 0 {
pipeline.register
}
pipeline.terminator iter_args(), results() : () -> ()
@ -42,7 +42,7 @@ func.func @boolean_condition() {
pipeline.while II = 1 iter_args(%arg0 = %c0_i32) : (i32) -> () {
pipeline.register %arg0 : i32
} do {
pipeline.stage start = 0 {
pipeline.while.stage start = 0 {
pipeline.register
}
pipeline.terminator iter_args(), results() : () -> ()
@ -67,7 +67,7 @@ func.func @only_stages() {
func.func @only_stages() {
%false = arith.constant 0 : i1
// expected-error @+1 {{'pipeline.while' op stages may only contain 'pipeline.stage' or 'pipeline.terminator' ops, found %1 = "arith.addi"(%arg0, %arg0) : (i1, i1) -> i1}}
// expected-error @+1 {{'pipeline.while' op stages may only contain 'pipeline.while.stage' or 'pipeline.terminator' ops, found %1 = "arith.addi"(%arg0, %arg0) : (i1, i1) -> i1}}
pipeline.while II = 1 iter_args(%arg0 = %false) : (i1) -> () {
pipeline.register %arg0 : i1
} do {
@ -84,7 +84,7 @@ func.func @mismatched_register_types() {
pipeline.while II = 1 iter_args(%arg0 = %false) : (i1) -> () {
pipeline.register %arg0 : i1
} do {
%0 = pipeline.stage start = 0 {
%0 = pipeline.while.stage start = 0 {
// expected-error @+1 {{'pipeline.register' op operand types ('i1') must match result types ('i2')}}
pipeline.register %arg0 : i1
} : i2
@ -100,7 +100,7 @@ func.func @mismatched_iter_args_types() {
pipeline.while II = 1 iter_args(%arg0 = %false) : (i1) -> () {
pipeline.register %arg0 : i1
} do {
pipeline.stage start = 0 {
pipeline.while.stage start = 0 {
pipeline.register
}
// expected-error @+1 {{'pipeline.terminator' op 'iter_args' types () must match pipeline 'iter_args' types ('i1')}}
@ -116,10 +116,10 @@ func.func @invalid_iter_args() {
pipeline.while II = 1 iter_args(%arg0 = %false) : (i1) -> (i1) {
pipeline.register %arg0 : i1
} do {
pipeline.stage start = 0 {
pipeline.while.stage start = 0 {
pipeline.register
}
// expected-error @+1 {{'pipeline.terminator' op 'iter_args' must be defined by a 'pipeline.stage'}}
// expected-error @+1 {{'pipeline.terminator' op 'iter_args' must be defined by a 'pipeline.while.stage'}}
pipeline.terminator iter_args(%false), results() : (i1) -> ()
}
return
@ -132,7 +132,7 @@ func.func @mismatched_result_types() {
pipeline.while II = 1 iter_args(%arg0 = %false) : (i1) -> (i1) {
pipeline.register %arg0 : i1
} do {
%0 = pipeline.stage start = 0 {
%0 = pipeline.while.stage start = 0 {
pipeline.register %arg0 : i1
} : i1
// expected-error @+1 {{'pipeline.terminator' op 'results' types () must match pipeline result types ('i1')}}
@ -148,10 +148,10 @@ func.func @invalid_results() {
pipeline.while II = 1 iter_args(%arg0 = %false) : (i1) -> (i1) {
pipeline.register %arg0 : i1
} do {
%0 = pipeline.stage start = 0 {
%0 = pipeline.while.stage start = 0 {
pipeline.register %arg0 : i1
} : i1
// expected-error @+1 {{'pipeline.terminator' op 'results' must be defined by a 'pipeline.stage'}}
// expected-error @+1 {{'pipeline.terminator' op 'results' must be defined by a 'pipeline.while.stage'}}
pipeline.terminator iter_args(%0), results(%false) : (i1) -> (i1)
}
return
@ -164,8 +164,8 @@ func.func @negative_start() {
pipeline.while II = 1 iter_args(%arg0 = %false) : (i1) -> () {
pipeline.register %arg0 : i1
} do {
// expected-error @+1 {{'pipeline.stage' op 'start' must be non-negative}}
%0 = pipeline.stage start = -1 {
// expected-error @+1 {{'pipeline.while.stage' op 'start' must be non-negative}}
%0 = pipeline.while.stage start = -1 {
pipeline.register %arg0 : i1
} : i1
pipeline.terminator iter_args(%0), results() : (i1) -> ()
@ -180,11 +180,11 @@ func.func @non_monotonic_start0() {
pipeline.while II = 1 iter_args(%arg0 = %false) : (i1) -> () {
pipeline.register %arg0 : i1
} do {
%0 = pipeline.stage start = 0 {
%0 = pipeline.while.stage start = 0 {
pipeline.register %arg0 : i1
} : i1
// expected-error @+1 {{'pipeline.stage' op 'start' must be after previous 'start' (0)}}
%1 = pipeline.stage start = 0 {
// expected-error @+1 {{'pipeline.while.stage' op 'start' must be after previous 'start' (0)}}
%1 = pipeline.while.stage start = 0 {
pipeline.register %0 : i1
} : i1
pipeline.terminator iter_args(%1), results() : (i1) -> ()
@ -199,14 +199,14 @@ func.func @non_monotonic_start1() {
pipeline.while II = 1 iter_args(%arg0 = %false) : (i1) -> () {
pipeline.register %arg0 : i1
} do {
%0 = pipeline.stage start = 0 {
%0 = pipeline.while.stage start = 0 {
pipeline.register %arg0 : i1
} : i1
%1 = pipeline.stage start = 1 {
%1 = pipeline.while.stage start = 1 {
pipeline.register %0 : i1
} : i1
// expected-error @+1 {{'pipeline.stage' op 'start' must be after previous 'start' (1)}}
%2 = pipeline.stage start = 0 {
// expected-error @+1 {{'pipeline.while.stage' op 'start' must be after previous 'start' (1)}}
%2 = pipeline.while.stage start = 0 {
pipeline.register %1 : i1
} : i1
pipeline.terminator iter_args(%2), results() : (i1) -> ()

43
test/Dialect/Pipeline/round-trip.mlir
View File

@ -15,15 +15,15 @@ func.func @test1(%arg0: memref<?xi32>) -> i32 {
pipeline.register %1 : i1
// CHECK: } do {
} do {
// CHECK: pipeline.stage start = 0 {
%1:2 = pipeline.stage start = 0 {
// CHECK: pipeline.while.stage start = 0 {
%1:2 = pipeline.while.stage start = 0 {
%3 = arith.addi %arg1, %c1 : index
%4 = memref.load %arg0[%arg1] : memref<?xi32>
// CHECK: pipeline.register {{.+}} : {{.+}}
// CHECK-NEXT: } : index, i32
pipeline.register %3, %4 : index, i32
} : index, i32
%2 = pipeline.stage start = 1 {
%2 = pipeline.while.stage start = 1 {
%3 = arith.addi %1#1, %arg2 : i32
pipeline.register %3 : i32
} : i32
@ -46,26 +46,26 @@ func.func @test2(%arg0: memref<?xi32>, %arg1: memref<?xi32>) {
%0 = arith.cmpi ult, %arg2, %c10 : index
pipeline.register %0 : i1
} do {
%0:4 = pipeline.stage start = 0 {
%0:4 = pipeline.while.stage start = 0 {
%4 = arith.addi %arg2, %c1 : index
%5 = memref.load %arg0[%arg2] : memref<?xi32>
%6 = arith.cmpi uge, %arg2, %c3 : index
pipeline.register %arg2, %4, %5, %6 : index, index, i32, i1
} : index, index, i32, i1
// CHECK: pipeline.stage start = 1 when %0#3
%1:3 = pipeline.stage start = 1 when %0#3 {
// CHECK: pipeline.while.stage start = 1 when %0#3
%1:3 = pipeline.while.stage start = 1 when %0#3 {
%4 = arith.subi %0#0, %c3 : index
pipeline.register %0#2, %0#3, %4 : i32, i1, index
} : i32, i1, index
%2:4 = pipeline.stage start = 2 when %1#1 {
%2:4 = pipeline.while.stage start = 2 when %1#1 {
%4 = memref.load %arg0[%1#2] : memref<?xi32>
pipeline.register %1#0, %1#1, %1#2, %4 : i32, i1, index, i32
} : i32, i1, index, i32
%3:3 = pipeline.stage start = 3 when %2#1 {
%3:3 = pipeline.while.stage start = 3 when %2#1 {
%4 = arith.addi %2#0, %2#3 : i32
pipeline.register %2#1, %2#2, %4 : i1, index, i32
} : i1, index, i32
pipeline.stage start = 5 when %3#0 {
pipeline.while.stage start = 5 when %3#0 {
memref.store %3#2, %arg1[%3#1] : memref<?xi32>
pipeline.register
}
@ -74,6 +74,7 @@ func.func @test2(%arg0: memref<?xi32>, %arg1: memref<?xi32>) {
return
}
// CHECK-LABEL: func.func @test3
func.func @test3(%arg0: memref<?xi32>) {
%c0 = arith.constant 0 : index
%c1 = arith.constant 1 : index
@ -89,7 +90,7 @@ func.func @test3(%arg0: memref<?xi32>) {
%3 = arith.cmpi ult, %arg1, %c10 : index
pipeline.register %3 : i1
} do {
%3:5 = pipeline.stage start = 0 {
%3:5 = pipeline.while.stage start = 0 {
%5 = arith.addi %arg1, %c1 : index
%6 = memref.load %2[%c0] : memref<1xi32>
%7 = memref.load %1[%c0] : memref<1xi32>
@ -97,13 +98,13 @@ func.func @test3(%arg0: memref<?xi32>) {
%9 = memref.load %arg0[%arg1] : memref<?xi32>
pipeline.register %5, %6, %7, %8, %9 : index, i32, i32, i32, i32
} : index, i32, i32, i32, i32
%4 = pipeline.stage start = 1 {
%4 = pipeline.while.stage start = 1 {
memref.store %3#2, %2[%c0] : memref<1xi32>
memref.store %3#3, %1[%c0] : memref<1xi32>
%5 = arith.addi %3#1, %3#4 : i32
pipeline.register %5 : i32
} : i32
pipeline.stage start = 2 {
pipeline.while.stage start = 2 {
memref.store %4, %0[%c0] : memref<1xi32>
pipeline.register
}
@ -112,6 +113,7 @@ func.func @test3(%arg0: memref<?xi32>) {
return
}
// CHECK-LABEL: func.func @test4
func.func @test4(%arg0: memref<?xi32>, %arg1: memref<?xi32>) {
%c0 = arith.constant 0 : index
%c1 = arith.constant 1 : index
@ -125,21 +127,21 @@ func.func @test4(%arg0: memref<?xi32>, %arg1: memref<?xi32>) {
%0 = arith.cmpi ult, %arg2, %c10 : index
pipeline.register %0 : i1
} do {
%0:2 = pipeline.stage start = 0 {
%0:2 = pipeline.while.stage start = 0 {
%3 = arith.addi %arg2, %c1 : index
%4 = memref.load %arg1[%arg2] : memref<?xi32>
%5 = arith.index_cast %4 : i32 to index
pipeline.register %3, %5 : index, index
} : index, index
%1:2 = pipeline.stage start = 1 {
%1:2 = pipeline.while.stage start = 1 {
%3 = memref.load %arg0[%0#1] : memref<?xi32>
pipeline.register %0#1, %3 : index, i32
} : index, i32
%2:2 = pipeline.stage start = 2 {
%2:2 = pipeline.while.stage start = 2 {
%3 = arith.addi %1#1, %c1_i32 : i32
pipeline.register %1#0, %3 : index, i32
} : index, i32
pipeline.stage start = 4 {
pipeline.while.stage start = 4 {
memref.store %2#1, %arg0[%2#0] : memref<?xi32>
pipeline.register
}
@ -148,6 +150,7 @@ func.func @test4(%arg0: memref<?xi32>, %arg1: memref<?xi32>) {
return
}
// CHECK-LABEL: func.func @test5
func.func @test5(%arg0: memref<?xi32>) {
%c1 = arith.constant 1 : index
%c2 = arith.constant 2 : index
@ -160,18 +163,18 @@ func.func @test5(%arg0: memref<?xi32>) {
%0 = arith.cmpi ult, %arg1, %c10 : index
pipeline.register %0 : i1
} do {
%0 = pipeline.stage start = 0 {
%0 = pipeline.while.stage start = 0 {
%2 = arith.subi %arg1, %c2 : index
%3 = memref.load %arg0[%2] : memref<?xi32>
pipeline.register %3 : i32
} : i32
%1:2 = pipeline.stage start = 1 {
%1:2 = pipeline.while.stage start = 1 {
%2 = arith.subi %arg1, %c1 : index
%3 = memref.load %arg0[%2] : memref<?xi32>
%4 = arith.addi %arg1, %c1 : index
pipeline.register %3, %4 : i32, index
} : i32, index
pipeline.stage start = 2 {
pipeline.while.stage start = 2 {
%2 = arith.addi %0, %1#0 : i32
memref.store %2, %arg0[%arg1] : memref<?xi32>
pipeline.register
@ -187,7 +190,7 @@ func.func @trip_count_attr() {
pipeline.while II = 1 trip_count = 3 iter_args(%arg0 = %false) : (i1) -> () {
pipeline.register %arg0 : i1
} do {
%0 = pipeline.stage start = 0 {
%0 = pipeline.while.stage start = 0 {
pipeline.register %arg0 : i1
} : i1
pipeline.terminator iter_args(%0), results() : (i1) -> ()