Start of support for building specialized software APIs!
- Create an op to hold metadata about services being implemented.
- Create them when we create the implementation request.
- Copy them up the instance hierarchy modifying the 'path' as they get moved up.
- Rename the capnp schema pass to the more generic "emit collateral" pass.
- Emit the service hierarchy information for the top levels in said pass.
This PR relaxes the downward only constraint on the RefType flow.
After this change,
- Modules can have input ports of `RefType`
- Instance ops can connect RefType input/output ports to module input/output
ports according to connect semantics.
- There is no constraint to where a `ref.resolve` can occur relative to `ref.send`
in the instance hierarchy
There are no additional verifiers currently added to constraint the `RefType`
flow, but the LowerXMR pass must error out, if multiply instantiated modules
with `RefType` ports are encountered.
This commit fixes a faulty guard mux input order in the feed-forward task pipelining transformation.
Instead of wrongly assuming a given relation between the mux input order and the cmerge inputs, it has to be checked for each case separately.
The provided test was affected by this faulty ordering and thus didn't terminate.
Use the emitc.include operation to add includes during lowering or transformations instead of hardcoding them in the printer. Add basic support in HWToSystemC and ExportSystemC.
This now tracks when randomized registers exceed a threshold, and
splits them up into multiple registers. This is intended to work
around register size limits in simulators that may be exceeded by
using a single large register to hold all of the random bits for each
module.
Fix a bug in FIRRTL register randomization where a canonicalizer was not
copying over register randomization information. This plugs a hole
where registers that fit a certain pattern could escape stable
randomization.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This commit introduces the base classes and utilities to implement
emission patterns and an emission printer which takes the role of a
driver that can be called in a circt-translate pass. Also includes
emission patterns for the builtin module and SCModule operations to
(1) allow to implement some basic unit and integration tests
(2) show the reviewer how emission patterns look like using this
infrastructure.
Note: when deleting dead ports, IMDCE introduces temporary wires
for the ports (inside the module) and at points of instantiation.
These are invalid for ref type, which isn't ideal, but they will be erased.
In one case this is not temporary, which this checks for,
the case where an output ref port is alive but not used by instantiators.
This commit adds a new pass LowerXMRPass.
The LowerXMRPass replaces every RefResolveOp with a verbatim expr op encoding
the corresponding XMR. The pass also removes every value of RefType and its
uses from the circuit.
This is a dataflow analysis over a very constrained RefType. Domain of the
dataflow analysis is the set of all RefSendOp. Essentially every RefType
value must be mapped to one and only one RefSendOp. The analysis propagates
the reachable RefSendOp to every value of RefType across modules. The
RefResolveOp is the final leaf into which the dataflow must flow into.
Due to the downward only reference constraint on XMRs, the post order traversal
ensures that the RefSendOp will be encountered before any user of the
RefType value. The pass fails and errors out if every "live" RefType value is
not mapped to a unique RefSendOp.
This adds a pass that collects all registers in each module, computes
how many bits of random data should be used to initialize them, and
saves this information for each module and register. In FirRegLower,
this is used to create one large random register per module, and
select out the appropriate bits for each register in the initial
block. This ensures the same large random register is created, and the
same bits are always selected for the same register, regardless of
optimizations that may remove registers.
There is basic support for none-typed channels, and a simple test. But
upon using none-typed channels for a more complex Handshake circuit,
it became apparent that the ESI lowering for none-typed ports was
missing a couple special cases. This includes a reduced test case and
the fixes I found necessary.
This comit switches ExportVerilog emission mode to new simplified version by default. `useOldEmissionMode` flag is added to use the old emission mode. If there is no problem for a few weeks, I'd like to entirely deprecate old emission implementation. Original proposal of ExportVerilog simplification is here: https://discourse.llvm.org/t/exportverilog-simplification-for-pretty-printing-output-verilog/63363
There should be differences in output verilog, specifically:
* Some whitespace changes in wire and reg declarations.
* There is no forward declaration anymore.
* Automatic logic variables get less inlined to declarations compared to the old mode. This is because of the current limitation of the analysis of inlinability.
* More assignments are inlined into declarations.
If there is an issue with new emission mode, you can use `--lowering-options=useOldEmissionMode`.
This PR introduces two operations to handle `RefType`.
The `RefType` is used to represent dataflow and the following operations
are added to make the dataflow relations explicit.
- RefSendOp
- Takes as input a `BaseType` and returns a `RefType`
- Used to send a read-only Reference handle of a local value.
- Represents the source of a dataflow by getting it's reference.
- RefResolveOp
- Takes as input a `RefType` and returns a `BaseType`
- Represents the sink of a dataflow from the reference handle
- The `RefType` is constrained to express a "single source to
one-or-more sink" dataflow
- Hence, multiple `RefResolveOp`s can be remotely connected to a single
`RefSendOp`.
- If the Reference ops are lowered to cross-module-reference, then it
represents the location of the XMR.
This commit also adds few lit tests to verify proper errors for the constraints
on the Reference ops and the `ref.mlir` to demonstrate the usage of
Reference ops, it does not check for any output, just that there are no errors.
`ref.mlir` can possibly be removed later when other passes handling the
Reference ops are introduced.
Co-authored-by: Will Dietz <will.dietz@sifive.com>
Remove the current port direction attribute and enum and use types to
represent the port direction. Reuse the PortInfo struct and enum of the
HW dialect to represent the port direction in CPP code when MLIR types
aren't that well suited. The rational is that these constructs are the
same across multiple dialects and should be part of the ModuleLike
interface to be reused by all module ops implementing the HWModuleLike
interface. Providing getters and builders that accept these port
direction/port info struct makes conversion between module ops that
implement HWModuleLike very convenient. This PR also implements that
interface for SystemC modules.
Also switch over to use the module_like and function_like parser and
printer utilities and add support for module visibility and argument
attributes.
Firrtl spec 1.1.0 added version identifiers to the fir file. Update the parse to parse these. Currently nothing is done with the version after parsing.
This implements a mechanism to inline blocking assignments into automatic logic
declarations in the new emission mode.
We can inline blocking assignment into automatic logic declrations if:
1. There exists a single blocking assignment which dominates all users of logic reads.
2. The source value of the assign can be inlined into the declaration. This is checked by `isExpressionEmittedInlineIntoProceduralDeclaration`.
Allow users to request bidirectional channels (InOut). Decomposes into
one `to_server` and one `to_client` request. Cosim will detect that and
wire them up to the same endpoint.
This commit first fixes incorrect inlining issue( https://github.com/llvm/circt/issues/3603) of automatic logic by restricting `isExpressionEmittedInlineIntoProceduralDeclaration` for read_inout op. More specifically, a read from wire is fine but we have to be more careful about reads from reg and logic because they can be modified with blocking assignments. This commit changes `isExpressionEmittedInlineIntoProceduralDeclaration` to check users of reg or logic and ensure that there is no blocking assignment.
The `msft.hlc.linear` operation defines a linear datapath. It serves as a container for `hw`, `comb` and `msft` operations, with the following restrictions:
- Not graph-like - only SSA def-use chains are allowed.
- `seq` ops are not allowed.
Adds the reference type, such as `firrtl.ref<uint<1>>`.
Used for remote reads and writes of the wrapped base type.
Parameterized over the referenced base type,
which must be passive and for now must also be ground.
Not a base type.
Values of this type are used to capture dataflow paths,
and do not represent a circuit element or entity.
Co-authored-by: Prithayan Barua <prithayan@gmail.com>
When printing the error message for deduplication failure, the error
printed for a stack of error messages is quite large and hard to read.
This makes an incremental improvement to the stack of error messages.
The most important improvement is that it prints as a single diagnostic
with a single `error:` emitted.
Before:
```
design.fir:1:1: error: module "Top0" not deduplicated with "Top1"
circuit Top :
^
design.scala:135:24: note: first instance targets module "Mid0"
design.scala:135:24: note: second instance targets module "Mid1"
design.fir:4395809:10: error: module "Mid0" not deduplicated with "MId1"
module Mid0:
^
design.scala:64:9: note: first operation has attribute 'message' with value "Assertion failed: 0"
design.scala:64:9: note: second operation has value "Assertion failed: 1"
```
After:
```
design.fir:1:1: error: module "Top0" not deduplicated with "Top1"
circuit Top :
^
design.fir:1:1: note: in instance "mid0" of "Mid0", and instance "mid1" of "Mid1"
design.scala:64:9: note: first operation has attribute 'message' with value "Assertion failed: 0"
design.scala:64:9: note: second operation has value "Assertion failed: 1"
```
This PR makes IMDCE propagate constant output ports to caller sides before
actually performing dataflow analysis so that we can eliminate constant output ports.
This representation and conversion aren't being used, and never
connected to Verilog output. The newer PipelineWhileOp could subsume
this use-case, and further evolution is coming to this dialect, so it
seems like a good time to clean out the older parts that aren't used.
This adds support for aggregate typed registers to the SFC compat pass.
SFC Compat looks at the values which are connected to registers; if they
are all invalid the reset can be removed, and resets for async registers
require a constant reset value.
Previously, this used the function `getModuleScopedDriver` which only
handles ground types. This creates a function `walkDrivers` which
performs a similar operation, but applies a call back when it finds
which fields of the aggregate is driven by some other value. Since the
source value and the the destination value might both be aggregates, the
callback uses FieldRefs to indicate the field.
- Simplified chains of inject ops into struct creates if all fields set
- Eliminated injects which are overwritten by other injects
- Canonicalized concatenation of array creates into a single array create
- Converted slices of concatenations into concatenations of slices
- Pushed array gets into slices and concatenations
- Merged a slice of a slice into a single slice
- Converted single-element slices to an array creation with a single element
- Simplified slices of array creates
This commit fixes a bug in the feed forward task pipelining transformation. A mux does not select its results with the same indexing as a control branch does, thus the boolean value requires negation.
* Bump LLVM
Bump LLVM to the current top-of-tree.
This requires changing a few `Attribute`s to the new `TypedAttr`
interface, since attributes no longer carry a type by default. We rely
on this type in quite a few places in the CIRCT codebase, which required
a switch over to `TypedAttr`.
See: https://reviews.llvm.org/D130092
Co-authored-by: John Demme <john.demme@microsoft.com>
This commit adds a transformation to ensure correct task pipelining.
For each split and merge block pair, it inserts a mechanism that ensures that the order of the threads is preserved.
Update the port symbol from StringAttr to InnerSymAttr.
This commit replaces empty string with Null attribute to denote
ports with no symbol and then use an empty InnerSymAttr when setting
the portSym attribute, because array attribute elements cannot be null.
FModuleLike interface now returns a null Attribute if the corresponding port
symbol does not exist. So, all the users of getPortSymbolAttr must check for
null instead of empty string.
The fixupPortSymsArray is used to replace any null entry in the port symbols
array with an empty InnerSymAttr, because its illegal to store Null attribute
Also added an error in LowerToHW, if there is any field sensitive symbol,
because HW dialect cannot handle them yet.
This fixes a name collision issue https://github.com/llvm/circt/issues/3607 when hw.verilogName
is pre-defined before ExportVerilog. If verilogName attr is attached to a declaration already,
it's necessary to force the name to the op. This PR changes `GlobalNameResolver::legalizeModuleNames`
to register used names first, and then legalize the declaration names.
Related PR: https://github.com/llvm/circt/pull/2104Close#3607.
It is probably fair to conclude that naming this dialect `StaticLogic` has been a pain point for a while. This commit proposes a dialect renaming to `Pipeline`, for a couple of reaons:
1. So far, we've only been working with pipeline abstractions within this dialect.
2. Pipeline representations aren't necessarily statically scheduled - we plan on adding switches to select between latency sensitive and latency insensitive lowerings of pipelines.
This name change does not preclude renamings in the future if we want to fit more stuff into this dialect. Personally, i think it is prudent to maintain a dialect name which reflects what's actually being done within the dialect, as well as the (near/mid/"someone actually intends to work on this"-term) future plans for the dialect.
Fixes#3635. Adds signature conversion for `hw::HWModuleOp,hw:HWExternalModuleOp` (`mlir::populateFunctionOpInterfaceTypeConversionPattern` unfortunately can't be provided an interface, i.e. `HWModuleLike`) as well as conversions for 'other' operations which we expect to be mixed in with `hwarith` operations.
Morten Borup Petersen