mirror of https://github.com/llvm/circt.git
223 lines
7.0 KiB
MLIR
223 lines
7.0 KiB
MLIR
// RUN: circt-opt --llhd-temporal-code-motion %s | FileCheck %s
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hw.module @basic(in %cond: i1) {
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%false = hw.constant false
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%true = hw.constant true
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%c0_i4 = hw.constant 0 : i4
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%c0_i5 = hw.constant 0 : i5
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// CHECK: [[V0:%.+]] = llhd.constant_time <0ns, 1d, 0e>
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// CHECK: [[V1:%.+]] = llhd.constant_time <0ns, 0d, 1e>
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%0 = llhd.constant_time <0ns, 1d, 0e>
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%1 = llhd.constant_time <0ns, 0d, 1e>
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// CHECK: %c = llhd.sig
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// CHECK: %d = llhd.sig
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// CHECK: %e = llhd.sig
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// CHECK: %f = llhd.sig
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// CHECK: %g = llhd.sig
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// CHECK: %h = llhd.sig
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// CHECK: %k = llhd.sig
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// CHECK: %l = llhd.sig
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// CHECK: %m = llhd.sig
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// CHECK: %n = llhd.sig
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// CHECK: %o = llhd.sig
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%c = llhd.sig %false : i1
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%d = llhd.sig %false : i1
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%e = llhd.sig %false : i1
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%f = llhd.sig %false : i1
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%g = llhd.sig %c0_i4 : i4
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%h = llhd.sig %c0_i4 : i4
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%k = llhd.sig %c0_i5 : i5
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%l = llhd.sig %c0_i5 : i5
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%m = llhd.sig %c0_i5 : i5
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%n = llhd.sig %c0_i5 : i5
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%o = llhd.sig %c0_i5 : i5
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%prb_k = llhd.prb %k : !hw.inout<i5>
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%prb_c = llhd.prb %c : !hw.inout<i1>
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%prb_e = llhd.prb %e : !hw.inout<i1>
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%prb_h = llhd.prb %h : !hw.inout<i4>
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%prb_d = llhd.prb %d : !hw.inout<i1>
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%prb_f = llhd.prb %f : !hw.inout<i1>
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%prb_g = llhd.prb %g : !hw.inout<i4>
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// COM: Check that an auxillary block is created and all drives are moved to
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// COM: the exit block with the correct enable condition
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// CHECK: llhd.process
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llhd.process {
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// CHECK: cf.br ^[[BB1:.+]]
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cf.br ^bb1
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// CHECK: ^[[BB1]]:
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^bb1:
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// CHECK: llhd.wait ({{.*}}), ^[[BB2:.+]]
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llhd.wait (%prb_k, %prb_c, %prb_e, %prb_h, %prb_d, %prb_f, %prb_g : i5, i1, i1, i4, i1, i1, i4), ^bb2
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// CHECK: ^[[BB2]]:
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^bb2:
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// CHECK: [[V14:%.+]] = llhd.prb %k
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// CHECK: [[V15:%.+]] = llhd.prb %c
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// CHECK: [[V16:%.+]] = llhd.prb %e
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// CHECK: [[V17:%.+]] = llhd.prb %h
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// CHECK: [[V18:%.+]] = comb.concat %false{{.*}}, [[V17]] : i1, i4
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// CHECK: [[V19:%.+]] = llhd.prb %d
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// CHECK: [[V20:%.+]] = llhd.prb %f
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// CHECK: [[V21:%.+]] = llhd.prb %k
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// CHECK: [[V22:%.+]] = llhd.prb %g
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// CHECK: [[V23:%.+]] = comb.concat %false{{.*}}, [[V22]] : i1, i4
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// CHECK: [[V24:%.+]] = comb.sub [[V21]], [[V23]] : i5
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// CHECK: [[V25:%.+]] = llhd.prb %k
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// CHECK: [[V26:%.+]] = llhd.prb %g
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// CHECK: [[V27:%.+]] = comb.concat %false{{.*}}, [[V26]] : i1, i4
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// CHECK: [[V28:%.+]] = comb.add [[V25]], [[V27]] : i5
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%25 = llhd.prb %k : !hw.inout<i5>
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llhd.drv %k, %25 after %1 : !hw.inout<i5>
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%26 = llhd.prb %c : !hw.inout<i1>
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%27 = llhd.prb %e : !hw.inout<i1>
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%28 = llhd.prb %h : !hw.inout<i4>
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%29 = comb.concat %false, %28 : i1, i4
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%30 = llhd.prb %d : !hw.inout<i1>
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%31 = llhd.prb %f : !hw.inout<i1>
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%32 = llhd.prb %k : !hw.inout<i5>
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%33 = llhd.prb %g : !hw.inout<i4>
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%34 = comb.concat %false, %33 : i1, i4
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%35 = comb.sub %32, %34 : i5
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%36 = llhd.prb %k : !hw.inout<i5>
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%37 = llhd.prb %g : !hw.inout<i4>
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%38 = comb.concat %false, %37 : i1, i4
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%39 = comb.add %36, %38 : i5
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cf.cond_br %26, ^bb3, ^bb4
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^bb3:
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llhd.drv %l, %c0_i5 after %1 if %cond : !hw.inout<i5>
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cf.br ^bb1
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^bb4:
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cf.cond_br %27, ^bb5, ^bb6
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^bb5:
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llhd.drv %m, %29 after %1 : !hw.inout<i5>
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cf.br ^bb1
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^bb6:
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cf.cond_br %30, ^bb7, ^bb1
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^bb7:
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cf.cond_br %31, ^bb8, ^bb9
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^bb8:
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llhd.drv %n, %35 after %1 : !hw.inout<i5>
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cf.br ^bb1
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^bb9:
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llhd.drv %o, %39 after %1 : !hw.inout<i5>
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cf.br ^bb1
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// CHECK: llhd.drv %k, [[V14]] after [[V1]] if %true{{.*}} : !hw.inout<i5>
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// CHECK: [[V29:%.+]] = comb.and %true{{.*}}, [[V15]] : i1
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// CHECK: [[V30:%.+]] = comb.or %false{{.*}}, [[V29]] : i1
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// CHECK: [[V31:%.+]] = comb.and %cond, [[V30]] : i1
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// CHECK: llhd.drv %l, %c0_i5 after [[V1]] if [[V31]] : !hw.inout<i5>
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// CHECK: [[V33:%.+]] = comb.xor [[V15]], %true{{.*}} : i1
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// CHECK: [[V34:%.+]] = comb.and %true{{.*}}, [[V33]] : i1
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// CHECK: [[V35:%.+]] = comb.or %false{{.*}}, [[V34]] : i1
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// CHECK: [[V36:%.+]] = comb.and [[V35]], [[V16]] : i1
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// CHECK: [[V37:%.+]] = comb.or %false{{.*}}, [[V36]] : i1
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// CHECK: llhd.drv %m, [[V18]] after [[V1]] if [[V37]] : !hw.inout<i5>
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// CHECK: [[V40:%.+]] = comb.xor [[V16]], %true{{.*}} : i1
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// CHECK: [[V41:%.+]] = comb.and [[V35]], [[V40]] : i1
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// CHECK: [[V42:%.+]] = comb.or %false{{.*}}, [[V41]] : i1
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// CHECK: [[V43:%.+]] = comb.and [[V42]], [[V19]] : i1
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// CHECK: [[V44:%.+]] = comb.or %false{{.*}}, [[V43]] : i1
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// CHECK: [[V45:%.+]] = comb.and [[V44]], [[V20]] : i1
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// CHECK: [[V46:%.+]] = comb.or %false{{.*}}, [[V45]] : i1
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// CHECK: llhd.drv %n, [[V24]] after [[V1]] if [[V46]] : !hw.inout<i5>
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// CHECK: [[V49:%.+]] = comb.xor [[V20]], %true{{.*}} : i1
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// CHECK: [[V50:%.+]] = comb.and [[V44]], [[V49]] : i1
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// CHECK: [[V51:%.+]] = comb.or %false{{.*}}, [[V50]] : i1
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// CHECK: llhd.drv %o, [[V28]] after [[V1]] if [[V51]] : !hw.inout<i5>
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// CHECK: cf.br ^[[BB1]]
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}
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// COM: check drive coalescing behavior
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llhd.process {
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cf.br ^bb1
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^bb1:
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llhd.wait ^bb2
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^bb2:
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// CHECK: [[V20:%.+]] = llhd.prb %l
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// CHECK-NEXT: [[V21:%.+]] = llhd.prb %m
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%20 = llhd.prb %l : !hw.inout<i5>
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%21 = llhd.prb %m : !hw.inout<i5>
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// CHECK-NEXT: llhd.drv %k, [[V21]] after [[V1]] : !hw.inout<i5>
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llhd.drv %k, %20 after %1 : !hw.inout<i5>
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llhd.drv %k, %21 after %1 : !hw.inout<i5>
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// CHECK-NEXT: [[V22:%.+]] = comb.mux %cond, [[V21]], [[V20]]
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// CHECK-NEXT: llhd.drv %l, [[V22]] after [[V1]] : !hw.inout<i5>
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llhd.drv %l, %20 after %1 : !hw.inout<i5>
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llhd.drv %l, %21 after %1 if %cond : !hw.inout<i5>
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// CHECK-NEXT: [[V23:%.+]] = comb.xor %cond, %true
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// CHECK-NEXT: [[V24:%.+]] = comb.mux %cond, [[V21]], [[V20]]
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// CHECK-NEXT: [[V25:%.+]] = comb.or %cond, [[V23]]
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// CHECK-NEXT: llhd.drv %m, [[V24]] after [[V1]] if [[V25]] : !hw.inout<i5>
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%22 = comb.xor %cond, %true : i1
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llhd.drv %m, %20 after %1 if %22 : !hw.inout<i5>
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llhd.drv %m, %21 after %1 if %cond : !hw.inout<i5>
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// CHECK-NEXT: cf.br
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cf.br ^bb1
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}
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}
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// The following processes should stay unmodified, just make sure the pass doesn't crash on them
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// CHECK-LABEL: hw.module @more_than_one_wait
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hw.module @more_than_one_wait() {
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llhd.process {
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cf.br ^bb1
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^bb1:
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llhd.wait ^bb2
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^bb2:
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llhd.wait ^bb1
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}
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}
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// CHECK-LABEL: hw.module @more_than_two_TRs
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hw.module @more_than_two_TRs() {
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llhd.process {
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cf.br ^bb1
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^bb1:
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llhd.wait ^bb2
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^bb2:
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llhd.wait ^bb3
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^bb3:
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llhd.wait ^bb1
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}
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}
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// CHECK-LABEL: hw.module @more_than_one_TR_wait_terminator
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hw.module @more_than_one_TR_wait_terminator(in %cond: i1) {
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llhd.process {
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cf.br ^bb1
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^bb1:
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cf.cond_br %cond, ^bb2, ^bb3
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^bb2:
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llhd.wait ^bb4
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^bb3:
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llhd.wait ^bb4
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^bb4:
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cf.br ^bb1
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}
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}
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// CHECK-LABEL: @unsupportedLoop
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hw.module @unsupportedLoop() {
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// CHECK-NEXT: llhd.process {
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// CHECK-NEXT: cf.br ^bb
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// CHECK-NEXT: ^bb
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// CHECK-NEXT: llhd.wait ^bb
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// CHECK-NEXT: }
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llhd.process {
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cf.br ^bb1
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^bb1:
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llhd.wait ^bb1
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}
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hw.output
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}
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