Martin Erhart fe170f9194 [LLHD][Sig2Reg] Support some signal aliasing (#8261) ... Only handles integer signal slices for now. I think it makes sense to expand on that in future PRs (array, struct aliases, drives with enables, etc.)		2025-02-20 18:23:12 +00:00
..
desequentialization.mlir	[LLHD][Desequentialization] Drive after inferred register should have no delay	2025-02-05 12:13:51 +00:00
earlyCodeMotion.mlir	[LLHD] Let WaitOp observe plain values instead of signals (#7528)	2024-08-19 17:36:10 +01:00
memoryToBlockArgument.mlir	[LLHD] Let WaitOp observe plain values instead of signals (#7528)	2024-08-19 17:36:10 +01:00
processLowering.mlir	[LLHD] Make process lowering best-effort and allow constants from outside the region (#7617)	2024-09-24 13:26:32 +01:00
sig2reg.mlir	[LLHD][Sig2Reg] Support some signal aliasing (#8261)	2025-02-20 18:23:12 +00:00
sroa.mlir	[LLHD][HW] Implement SROA interfaces (#7672)	2024-10-07 19:46:31 +01:00
temporal-code-motion.mlir	[LLHD][TCM] Ignore processes with CFG loops within a TR (#8196)	2025-02-06 17:47:34 +00:00
totalFunctionInlining.mlir	[LLHD] Refactor llhd.proc and remove llhd.inst (#7357)	2024-07-19 21:18:07 +01:00