mirror of https://github.com/llvm/circt.git
93 lines
3.6 KiB
MLIR
93 lines
3.6 KiB
MLIR
// RUN: circt-opt -lower-firrtl-to-hw %s | FileCheck %s
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firrtl.circuit "Arithmetic" {
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// CHECK-LABEL: hw.module @Arithmetic
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firrtl.module @Arithmetic(in %uin3c: !firrtl.uint<3>,
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out %out0: !firrtl.uint<3>,
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out %out1: !firrtl.uint<4>,
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out %out2: !firrtl.uint<4>,
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out %out3: !firrtl.uint<1>) {
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%uin0c = firrtl.wire : !firrtl.uint<0>
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// CHECK-DAG: [[MULZERO:%.+]] = hw.constant 0 : i3
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%0 = firrtl.mul %uin0c, %uin3c : (!firrtl.uint<0>, !firrtl.uint<3>) -> !firrtl.uint<3>
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firrtl.connect %out0, %0 : !firrtl.uint<3>, !firrtl.uint<3>
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// Lowers to nothing.
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%m0 = firrtl.mul %uin0c, %uin0c : (!firrtl.uint<0>, !firrtl.uint<0>) -> !firrtl.uint<0>
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// Lowers to nothing.
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%node = firrtl.node %m0 : !firrtl.uint<0>
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// Lowers to nothing. Issue #429.
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%div = firrtl.div %node, %uin3c : (!firrtl.uint<0>, !firrtl.uint<3>) -> !firrtl.uint<0>
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// CHECK-DAG: %c0_i4 = hw.constant 0 : i4
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// CHECK-DAG: %false = hw.constant false
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// CHECK-NEXT: [[UIN3EXT:%.+]] = comb.concat %false, %uin3c : i1, i3
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// CHECK-NEXT: [[ADDRES:%.+]] = comb.add bin [[UIN3EXT]], %c0_i4 : i4
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%1 = firrtl.add %uin0c, %uin3c : (!firrtl.uint<0>, !firrtl.uint<3>) -> !firrtl.uint<4>
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firrtl.connect %out1, %1 : !firrtl.uint<4>, !firrtl.uint<4>
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%2 = firrtl.shl %node, 4 : (!firrtl.uint<0>) -> !firrtl.uint<4>
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firrtl.connect %out2, %2 : !firrtl.uint<4>, !firrtl.uint<4>
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// Issue #436
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%3 = firrtl.eq %uin0c, %uin0c : (!firrtl.uint<0>, !firrtl.uint<0>) -> !firrtl.uint<1>
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firrtl.connect %out3, %3 : !firrtl.uint<1>, !firrtl.uint<1>
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// CHECK: hw.output %c0_i3, [[ADDRES]], %c0_i4, %true
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}
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// CHECK-LABEL: hw.module private @Exotic
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firrtl.module private @Exotic(in %uin3c: !firrtl.uint<3>,
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out %out0: !firrtl.uint<3>,
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out %out1: !firrtl.uint<3>) {
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%uin0c = firrtl.wire : !firrtl.uint<0>
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// CHECK-DAG: = hw.constant true
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%0 = firrtl.andr %uin0c : (!firrtl.uint<0>) -> !firrtl.uint<1>
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// CHECK-DAG: = hw.constant false
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%1 = firrtl.xorr %uin0c : (!firrtl.uint<0>) -> !firrtl.uint<1>
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%2 = firrtl.orr %uin0c : (!firrtl.uint<0>) -> !firrtl.uint<1>
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// Lowers to the uin3 value.
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%3 = firrtl.cat %uin0c, %uin3c : (!firrtl.uint<0>, !firrtl.uint<3>) -> !firrtl.uint<3>
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firrtl.connect %out0, %3 : !firrtl.uint<3>, !firrtl.uint<3>
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// Lowers to the uin3 value.
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%4 = firrtl.cat %uin3c, %uin0c : (!firrtl.uint<3>, !firrtl.uint<0>) -> !firrtl.uint<3>
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firrtl.connect %out1, %4 : !firrtl.uint<3>, !firrtl.uint<3>
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// Lowers to nothing.
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%5 = firrtl.cat %uin0c, %uin0c : (!firrtl.uint<0>, !firrtl.uint<0>) -> !firrtl.uint<0>
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// CHECK: hw.output %uin3c, %uin3c : i3, i3
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}
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// CHECK-LABEL: hw.module private @Decls
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firrtl.module private @Decls(in %uin3c: !firrtl.uint<3>) {
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%sin0c = firrtl.wire : !firrtl.sint<0>
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%uin0c = firrtl.wire : !firrtl.uint<0>
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// Lowers to nothing.
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%wire = firrtl.wire : !firrtl.sint<0>
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firrtl.connect %wire, %sin0c : !firrtl.sint<0>, !firrtl.sint<0>
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// CHECK-NEXT: hw.output
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}
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// Check that a zero-width value shifted right produces a zero.
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// See: https://github.com/llvm/circt/issues/6652
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// CHECK-LABEL: hw.module @ShrZW
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firrtl.module @ShrZW(in %x: !firrtl.uint<0>, out %out: !firrtl.uint<1>) attributes {convention = #firrtl<convention scalarized>} {
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%0 = firrtl.shr %x, 5 : (!firrtl.uint<0>) -> !firrtl.uint<0>
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firrtl.connect %out, %0 : !firrtl.uint<1>, !firrtl.uint<0>
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// CHECK: %[[false:.+]] = hw.constant false
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// CHECK-NEXT: hw.output %false
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}
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}
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