mirror of https://github.com/llvm/circt.git
bd8e050044
Lower `firrtl.contract` to `verif.contract` ops. The lowering itself is pretty straightforward, since the ops are basically equivalent. The only exception are block arguments in FIRRTL that get replaced with op results in Verif due to the switch from an SSACFG region with dominance to a graph region. The block arguments require a slight change to how nested operations are handled by the pass. Currently, a post-order walk over the operations is used. This is problematic since the parent operation does not get an opportunity to lower its block arguments before its child operations are lowered, which may need access to those block arguments. Switching to a pre-order walk does not work, since that wouldn't allow us to modify the operations during the walk, which we obviously do during the lowering. This commit therefore adds a worklist that tracks operation ranges that are yet to be lowered. The worklist allows parent operations to lower themselves and any of their block arguments, and then add the nested regions, blocks, or operations onto the worklist for lowering. It's basically a pre-walk with the ability to mutate the parent operation before children are lowered. Block arguments are also no longer automatically assumed to be already lowered. This was only valid for modules, since we lower the module ports before we lower the module body. In case of ops like contracts, the block arguments still need to be lowered. To fix this, modules push a 1-1 mapping of their block arguments into the map of lowered values, which allows other ops to provide some other lowering for their block arguments. |
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| .. | ||
| emit-chisel-asserts-as-sva.mlir | ||
| errors.mlir | ||
| intrinsics-errors.mlir | ||
| intrinsics.mlir | ||
| lower-to-hw-errors.mlir | ||
| lower-to-hw-memories.mlir | ||
| lower-to-hw-module.mlir | ||
| lower-to-hw.mlir | ||
| module-hierarchy-file.mlir | ||
| zero-width.mlir | ||