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AIGToComb
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[AIGToComb] [circt-synth] Add a AIG to Comb conversion pass (#7742)
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2024-10-29 14:15:41 +09:00 |
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AffineToLoopSchedule
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[LoopSchedule] Move PipelineWhile and Related Ops from Pipeline to LoopSchedule (#4947)
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2023-04-18 11:56:07 -04:00 |
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ArcToLLVM
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Bump LLVM to 289b17635958d986b74683c932df6b1d12f37b70. (#8225)
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2025-02-13 14:32:11 -07:00 |
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CFToHandshake
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[Handshake] `StandardToHandshake` -> `CFToHandshake` (#5938)
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2023-08-25 09:24:26 +02:00 |
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CalyxToFSM
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[calyx] fix calyx canonicalization. (#7456)
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2024-08-10 10:02:08 -04:00 |
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CalyxToHW
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Add emission for calyx std_signext (#6285)
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2023-10-12 12:17:44 -04:00 |
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CombToAIG
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[CombToAIG] Add support for div/mod operations (#8130)
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2025-02-03 15:11:09 -08:00 |
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CombToArith
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[CombToArith] Fix coarsening of division by zero UB (#6945)
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2024-05-06 15:59:36 +02:00 |
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CombToSMT
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[CombToSMT] Register dependency on func (#7098)
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2024-05-28 21:46:54 +02:00 |
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ConvertToArcs
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[Seq][Arc] Allow seq.initial to take immutable operands. Add a cast operation (#7656)
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2024-10-04 02:20:12 +09:00 |
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DCToHW
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[DCtoHW] Some modules don't have bodies
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2024-11-26 21:58:11 +00:00 |
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ExportChiselInterface
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[ExportChiselInterface] Support probe types (#5497)
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2023-06-30 09:22:46 -06:00 |
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ExportVerilog
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[ExportVerilog] Treat verif.contract as no-op (#8143)
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2025-01-29 15:22:16 -08:00 |
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FIRRTLToHW
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[FIRRTL][LowerToHW] Lower contract ops (#8159)
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2025-02-07 15:34:34 -08:00 |
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FSMToSV
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[FSM][Emit] Convert the FSMToSV pass to use `emit` ops (#6828)
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2024-03-19 19:30:02 +02:00 |
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HWArithToHW
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[HWArith] Fix lowering to HW with type aliases
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2024-12-19 00:57:08 +00:00 |
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HWToBTOR2
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[HWToBTOR2] Fix incorrect le/ge predicate name emission (#8028)
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2025-01-04 21:14:21 +00:00 |
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HWToLLVM
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Bump LLVM (#7223)
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2024-06-26 13:19:37 -07:00 |
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HWToSMT
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[HWToSMT] Proper error message for 0-bit constants (#7727)
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2024-10-24 17:37:03 +01:00 |
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HWToSV
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[NFC][HW] Fix parsing of nullary hw.triggered ops (#7291)
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2024-07-09 17:51:03 +02:00 |
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HWToSystemC
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[HW] Change printer for modules (#6205)
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2023-09-28 16:30:15 -05:00 |
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HandshakeToDC
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[HandshakeToDC] Fix a bug in the sync conversion pattern
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2024-12-02 18:55:14 +00:00 |
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HandshakeToHW
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[Handshake] Adding func instance op for integration (#7812)
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2024-11-15 12:00:40 -08:00 |
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ImportVerilog
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[ImportVerilog] Fix bugs with constant folding (#8213)
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2025-02-10 12:02:29 +00:00 |
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LTLToCore
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[Seq][Arc] Allow seq.initial to take immutable operands. Add a cast operation (#7656)
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2024-10-04 02:20:12 +09:00 |
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LoopScheduleToCalyx
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[NFC] fix test comment.
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2025-01-10 08:55:35 -08:00 |
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MooreToCore
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[Moore] Mark wait_event with side-effect even if it is empty (#8220)
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2025-02-11 20:52:45 +00:00 |
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PipelineToHW
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[Pipeline] Make `reset` signal optional (#8104)
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2025-01-23 14:15:50 +01:00 |
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SCFToCalyx
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[SCFToCalyx] Update the lowering of SCF ParallelOp after AffineParallelUnroll pass (#8250)
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2025-02-18 13:32:43 -05:00 |
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SMTToZ3LLVM
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[SMT] Add bv2int op (#8049)
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2025-01-10 13:30:34 +00:00 |
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SeqToSV
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[SeqToSV] Put fragments on hw.module.generated
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2025-02-01 22:11:09 -05:00 |
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SimToSV
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[SimToSV] Add include guards to DPI import (#7459)
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2024-08-08 15:40:35 +09:00 |
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VerifToSMT
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Bump LLVM to 560b72c0408a8f7e4340a1d4197b164a14cd30b0. (#8043)
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2025-01-09 16:06:43 -07:00 |
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VerifToSV
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[HW] Change printer for modules (#6205)
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2023-09-28 16:30:15 -05:00 |
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