mirror of https://github.com/llvm/circt.git
150 lines
6.9 KiB
MLIR
150 lines
6.9 KiB
MLIR
// RUN: circt-opt %s -export-verilog -verify-diagnostics | FileCheck %s --strict-whitespace
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module {
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// CHECK-LABEL: interface data_vr;
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// CHECK: logic [31:0] data;
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// CHECK: logic valid;
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// CHECK: logic ready;
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// CHECK: logic [3:0][7:0] arrayData;
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// CHECK: logic [7:0] uarrayData[0:3];
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// CHECK: modport data_in(input data, input valid, output ready);
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// CHECK: modport data_out(output data, output valid, input ready);
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// CHECK: MACRO(data, valid, ready -- data_in)
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// CHECK: // logic /*Zero Width*/ zeroGround;
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// CHECK: // logic [3:0]/*Zero Width*/ zeroArray;
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// CHECK: // logic /*Zero Width*/ zeroUArray[0:3];
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// CHECK: endinterface
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// CHECK-EMPTY:
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sv.interface @data_vr {
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sv.interface.signal @data : i32
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sv.interface.signal @valid : i1
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sv.interface.signal @ready : i1
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sv.interface.signal @arrayData : !hw.array<4xi8>
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sv.interface.signal @uarrayData : !hw.uarray<4xi8>
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sv.interface.modport @data_in (input @data, input @valid, output @ready)
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sv.interface.modport @data_out (output @data, output @valid, input @ready)
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sv.verbatim "//MACRO({{0}}, {{1}}, {{2}} -- {{3}})"
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{symbols = [@data, @valid, @ready, @data_in]}
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sv.interface.signal @zeroGround : i0
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sv.interface.signal @zeroArray : !hw.array<4xi0>
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sv.interface.signal @zeroUArray : !hw.uarray<4xi0>
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}
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// CHECK-LABEL: interface struct_vr;
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// CHECK: struct packed {logic [6:0] foo; logic [4:0][15:0] bar; } data;
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// CHECK: logic valid;
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// CHECK: logic ready;
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// CHECK: modport data_in(input data, input valid, output ready);
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// CHECK: modport data_out(output data, output valid, input ready);
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// CHECK: endinterface
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// CHECK-EMPTY:
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sv.interface @struct_vr {
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sv.interface.signal @data : !hw.struct<foo: i7, bar: !hw.array<5 x i16>>
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sv.interface.signal @valid : i1
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sv.interface.signal @ready : i1
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sv.interface.modport @data_in (input @data, input @valid, output @ready)
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sv.interface.modport @data_out (output @data, output @valid, input @ready)
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}
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hw.module.extern @Rcvr (in %m: !sv.modport<@data_vr::@data_in>)
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// CHECK-LABEL: module Top
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hw.module @Top (in %clk: i1) {
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// CHECK: data_vr [[IFACE:.+]]();
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%iface = sv.interface.instance : !sv.interface<@data_vr>
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// CHECK: MACRO-Interface:data_vr
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sv.verbatim "//MACRO-Interface:{{0}}" {symbols = [@data_vr]}
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// CHECK: struct_vr [[IFACEST:.+]]();
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%structIface = sv.interface.instance : !sv.interface<@struct_vr>
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%ifaceInPort = sv.modport.get %iface @data_in :
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!sv.interface<@data_vr> -> !sv.modport<@data_vr::@data_in>
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// CHECK: Rcvr rcvr1 ({{.*}}//{{.+}}
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// CHECK: .m ([[IFACE]].data_in){{.*}}//{{.+}}
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// CHECK: );
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hw.instance "rcvr1" @Rcvr(m: %ifaceInPort: !sv.modport<@data_vr::@data_in>) -> ()
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// CHECK: Rcvr rcvr2 ({{.*}}//{{.+}}
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// CHECK: .m ([[IFACE]].data_in){{.*}}//{{.+}}
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// CHECK: );
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hw.instance "rcvr2" @Rcvr(m: %ifaceInPort: !sv.modport<@data_vr::@data_in>) -> ()
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%c1 = hw.constant 1 : i1
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// CHECK: assign iface.valid = 1'h1;
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sv.interface.signal.assign %iface(@data_vr::@valid) = %c1 : i1
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sv.always posedge %clk {
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%fd = hw.constant 0x80000002 : i32
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%validValue = sv.interface.signal.read %iface(@data_vr::@valid) : i1
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// CHECK: $fwrite(32'h80000002, "valid: %d\n", iface.valid);
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sv.fwrite %fd, "valid: %d\n" (%validValue) : i1
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// CHECK: assert(iface.valid);
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sv.assert %validValue, immediate
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sv.if %clk {
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%structDataSignal = sv.interface.signal.read %structIface(@struct_vr::@data) : !hw.struct<foo: i7, bar: !hw.array<5 x i16>>
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%structData = hw.struct_extract %structDataSignal["foo"] : !hw.struct<foo: i7, bar: !hw.array<5 x i16>>
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// CHECK: $fwrite(32'h80000002, "%d", [[IFACEST]].data.foo);
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sv.fwrite %fd, "%d"(%structData) : i7
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}
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}
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}
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// Next test case is related to:https://github.com/llvm/circt/issues/681
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// Rename keywords used in variable/module names
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// NOTE(fschuiki): Extern modules should trigger an error diagnostic if they
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// would cause a rename, but since the user supplies the module externally we
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// can't just rename it.
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hw.module.extern @regStuff (in %m: !sv.modport<@data_vr::@data_in>)
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// CHECK-LABEL: module Top2
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hw.module @Top2 (in %clk: i1) {
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// CHECK: data_vr [[IFACE:.+]]();{{.*}}//{{.+}}
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%iface = sv.interface.instance : !sv.interface<@data_vr>
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%ifaceInPort = sv.modport.get %iface @data_in :
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!sv.interface<@data_vr> -> !sv.modport<@data_vr::@data_in>
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// CHECK: regStuff rcvr1 ({{.*}}//{{.+}}
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// CHECK: .m ([[IFACE]].data_in){{.*}}//{{.+}}
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// CHECK: );
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hw.instance "rcvr1" @regStuff(m: %ifaceInPort: !sv.modport<@data_vr::@data_in>) -> ()
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// CHECK: regStuff rcvr2 ({{.*}}//{{.+}}
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// CHECK: .m ([[IFACE]].data_in){{.*}}//{{.+}}
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// CHECK: );
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hw.instance "rcvr2" @regStuff(m: %ifaceInPort: !sv.modport<@data_vr::@data_in>) -> ()
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}
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// https://github.com/llvm/circt/issues/724
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sv.interface @IValidReady_Struct {
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sv.interface.signal @data : !hw.struct<foo: !hw.array<384xi1>>
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}
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// CHECK-LABEL: module structs(
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// CHECK-NOT: wire [383:0] _tmp =
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// CHECK: wire struct packed {logic [383:0] foo; } _GEN
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// CHECK: endmodule
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hw.module @structs(in %clk: i1, in %rstn: i1) {
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%0 = sv.interface.instance name "iface" : !sv.interface<@IValidReady_Struct>
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sv.interface.signal.assign %0(@IValidReady_Struct::@data) = %s : !hw.struct<foo: !hw.array<384xi1>>
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%c0 = hw.constant 0 : i8
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%c64 = hw.constant 100000 : i64
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%16 = hw.bitcast %c64 : (i64) -> !hw.array<64xi1>
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%58 = hw.bitcast %c0 : (i8) -> !hw.array<8xi1>
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%90 = hw.array_concat %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %58, %16, %16 : !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<8xi1>, !hw.array<64xi1>, !hw.array<64xi1>
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%s = hw.struct_create (%90) : !hw.struct<foo: !hw.array<384xi1>>
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}
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// CHECK-LABEL: interface renameType;
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sv.interface @renameType {
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sv.interface.signal @data : !hw.struct<repeat: i1>
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// CHECK-NEXT: struct packed {logic repeat_0; } data;
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}
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// CHECK-LABEL: // interface with a comment
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// CHECK-NEXT: interface interfaceWithComment
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sv.interface @interfaceWithComment
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attributes {comment = "interface with a comment"} {}
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}
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