mirror of https://github.com/llvm/circt.git
44 lines
1.3 KiB
MLIR
44 lines
1.3 KiB
MLIR
// RUN: circt-opt --export-verilog --verify-diagnostics %s -o %t | FileCheck %s --strict-whitespace
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// CHECK-LABEL: module zeroWidthPAssign(
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// CHECK: always_ff @(posedge clk) begin
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// CHECK-NEXT: end
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hw.module @zeroWidthPAssign(in %arg0 : i0, in %clk: i1, out out: i0) {
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%0 = sv.reg {hw.verilogName = "_GEN"} : !hw.inout<i0>
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sv.alwaysff(posedge %clk) {
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sv.passign %0, %arg0 : i0
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}
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%1 = sv.read_inout %0 : !hw.inout<i0>
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hw.output %1 : i0
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}
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// CHECK-LABEL: module zeroWidthLogic(
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// CHECK-NOT: reg
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hw.module @zeroWidthLogic(in %arg0 : i0, in %sel : i1, in %clk : i1, out out : i0) {
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%r = sv.reg : !hw.inout<i0>
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%rr = sv.read_inout %r : !hw.inout<i0>
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%2 = comb.mux %sel, %rr, %arg0 : i0
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hw.output %2 : i0
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}
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// CHECK-LABEL: module Concat(
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hw.module @Concat(in %arg0 : i0, in %arg1 : i1, in %clk : i1, out out: i2) {
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// CHECK: assign out = {arg1, clk};
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%1 = comb.concat %arg0, %arg1, %clk : i0, i1, i1
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hw.output %1 : i2
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}
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// CHECK-LABEL: module icmp(
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hw.module @icmp(in %a : i0, out y: i1) {
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// CHECK: assign y = 1'h1;
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%0 = comb.icmp eq %a, %a : i0
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hw.output %0 : i1
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}
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// CHECK-LABEL: module parity(
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hw.module @parity(in %arg0 : i0, out out: i1) {
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// CHECK: assign out = 1'h0;
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%0 = comb.parity %arg0 : i0
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hw.output %0 : i1
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}
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