mirror of https://github.com/llvm/circt.git
64 lines
1.9 KiB
MLIR
64 lines
1.9 KiB
MLIR
// RUN: circt-opt --export-verilog %s | FileCheck %s
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// RUN: circt-opt --test-apply-lowering-options='options=mitigateVivadoArrayIndexConstPropBug' --export-verilog %s | FileCheck %s --check-prefix=FIXED
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// CHECK-LABEL: module Simple(
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// FIXED-LABEL: module Simple(
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hw.module @Simple(in %a : !hw.array<16xi1>, in %b : i4, out c: i1) {
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// CHECK: assign c = a[b + 4'h1];
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// FIXED: (* keep = "true" *)
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// FIXED-NEXT: wire [3:0] [[IDX0:.+]] = b + 4'h1;
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// FIXED-NEXT: assign c = a[[[IDX0]]];
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%c1_i4 = hw.constant 1 : i4
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%0 = comb.add %b, %c1_i4 : i4
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%1 = hw.array_get %a[%0] : !hw.array<16xi1>, i4
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hw.output %1 : i1
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}
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// CHECK: endmodule
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// FIXED: endmodule
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// CHECK-LABEL: module ExistingWire(
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// FIXED-LABEL: module ExistingWire(
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hw.module @ExistingWire(in %a: !hw.array<16xi1>, in %b : i4, out c: i1) {
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// CHECK: wire [3:0] existingWire = b + 4'h3;
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// CHECK-NEXT: assign c = a[existingWire];
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// FIXED: (* keep = "true" *)
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// FIXED-NEXT: wire [3:0] existingWire = b + 4'h3;
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// FIXED-NEXT: assign c = a[existingWire];
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%c1_i4 = hw.constant 3 : i4
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%0 = comb.add %b, %c1_i4 : i4
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%existingWire = sv.wire : !hw.inout<i4>
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sv.assign %existingWire, %0 : i4
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%1 = sv.read_inout %existingWire : !hw.inout<i4>
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%2 = hw.array_get %a[%1] : !hw.array<16xi1>, i4
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hw.output %2 : i1
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}
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// CHECK: endmodule
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// FIXED: endmodule
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// CHECK-LABEL: module ProceduralRegion(
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// FIXED-LABEL: module ProceduralRegion(
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hw.module @ProceduralRegion(in %a: !hw.array<16xi1>, in %b : i4) {
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// CHECK: magic(a[b + 4'h1]);
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// FIXED: initial begin
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// FIXED-NEXT: (* keep = "true" *)
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// FIXED-NEXT: automatic logic [3:0] [[IDX0:.+]] = b + 4'h1;
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// FIXED-NEXT: magic(a[[[IDX0]]]);
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// FIXED-NEXT: end
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%c1_i4 = hw.constant 1 : i4
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%0 = comb.add %b, %c1_i4 : i4
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sv.initial {
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%1 = hw.array_get %a[%0] : !hw.array<16xi1>, i4
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sv.verbatim "magic({{0}});" (%1): i1
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}
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}
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// CHECK: endmodule
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// FIXED: endmodule
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