mirror of https://github.com/llvm/circt.git
13 lines
469 B
MLIR
13 lines
469 B
MLIR
// RUN: circt-opt --export-verilog %s | FileCheck %s
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// CHECK-LABEL: module symbols
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// CHECK-NEXT: input baz /* #hw<innerSym@bazSym> */
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module attributes {circt.loweringOptions="printDebugInfo"} {
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hw.module @symbols(in %baz: i1 {hw.exportPort = #hw<innerSym@bazSym>}) {
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// CHECK: wire foo /* #hw<innerSym@fooSym> */;
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%foo = sv.wire sym @fooSym : !hw.inout<i1>
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// CHECK: reg bar /* #hw<innerSym@barSym> */;
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%bar = sv.reg sym @barSym : !hw.inout<i1>
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}
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}
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