mirror of https://github.com/llvm/circt.git
14 lines
450 B
MLIR
14 lines
450 B
MLIR
// RUN: circt-opt %s -export-verilog -verify-diagnostics | FileCheck %s
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// Test bug in function type conversion
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// CHECK-LABEL: InOutWire
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module attributes {circt.loweringOptions = "disallowExpressionInliningInPorts"} {
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hw.module.extern @Bar(inout %a: i1, out b: i1)
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hw.module private @InOutWire() {
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// CHECK: wire a;
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%a = sv.wire : !hw.inout<i1>
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// CHECK: .a (a),
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%bar.b = hw.instance "bar" @Bar(a: %a: !hw.inout<i1>) -> (b: i1)
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}
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}
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