This commit adds CSE after hw canonicalization to clean up values
created by canonicalization. Even though it will increase compile time slightly,
I believe it is very beneficial to run CSE again in terms of verilog qualify.
I have seen 20% simulation speed up for large designs.
This also closes#2449
Added a separate flag to dump the IR with `sv` ops, replacing `--ir-hw`.
From this point onwards, `--ir-hw` will dump IR in HW form, while `--ir-sv`
will include constructs (such as registers) expanded into SytemVerilog form.
Change the name of FIRRTL Dialect's RemoveResets pass to RemoveInvalid.
This is done in preparation to add functionality to RemoveResets to
remove all invalid values after it removes resets. In effect, this pass
is now an "invalid removal" pass.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This commit adds a few timing scope for FIPParser so that
we can profile elapsed times more precisely.
FIRParser is the most expensive pass in firtool which spends 30%
of whole time. This commit puts 3 nested timing scopes such as
"annotation parsing", "module parsing" and "circuit verification".
Change two usages of create_directory to create_directories as the
former will error if parent directories do not exist while the latter
will create parent directories.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
In a recent refactoring, firtool was split into two pass managers, so
we could stop before the "export" passes if any of the "lower" passes
failed. However, this neglected to include adding the
FirtoolPassInstrumentation to the "export" pass manager. This closes
https://github.com/llvm/circt/issues/2854.
This commit makes firtool print emit logs about parsing if
verbose-pass-executions option is enabled. Currently I just hard-coded
the logging messages to keep the implementation simple.
Example:
```
[firtool] Running fir parser
[firtool] -- Done in 0.056 sec
[firtool] ...
```
If questa or vivado are not found, `iverilog` is used to run supported tests. Tests which cannot be executed using this simulator can be disabled by adding `// DISABLED: ieee-sim-iverilog` or `// DISABLED: iverilog`.
Icarus verilog tests can be disabled altogether by passing `-DIVERILOG_DISABLE=ON` to cmake, similarly to other simulators.
resolvesllvm/circt#879
Remove all support for BlackBoxResourceAnno. This annotation was
deprecated in FIRRTL 1.5.0 and is no longer emitted by any Chisel APIs
as of Chisel 3.5.0.
Fixes#2785.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Change Grand Central Views to modify existing black boxes which are
instantiated in a companion so that they will be written to the Grand
Central extraction directory. This is done to match SFC behavior around
where black boxes are written.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Fix a bug when running `firtool --mlir-timing` where the timing
information of the second pass manager (which handles Verilog emission)
was being elided from the output.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This adds early returns with signalPassFailure when failure bubbles up
in the LowerToHW pass. In order to catch such failures and exit before
the ExportVerilog passes, the firtool pass manager is split into two
pipelines. The first pipeline handles the main lowering passes, and
only if those succeed, the second pipeline handles ExportVerilog.
The `ModuleExternalizer`, `InstanceStubber`, and `MemoryStubber`
reductions are pretty aggressive and usually do a good job at pruning
the non-interesting hierarchies of the design. Move these up such that
they run very early on, making subsequent fine-grained reductions able
to iterate a lot faster.
Add the `detach-subaccesses` reduction which replaces subaccesses on a
wire or register with a new wire of the subaccess' type. The reduction
is done on entire wires, if the only uses of those wires are
subaccesses. The original wire and all its subaccesses are deleted, such
that only the newly-created, detached wires are left. This has the
ability to dissolve large aggregate wires that are invalidate through
subaccesses, which the reducer cannot otherwise remove efficiently if
the wire type is non-passive.
This reduction greatly improves `circt-reduce`'s ability to deal with
inputs that have not seen type lowering.
Run inter-module constant propagation as part of the reduction process.
This can help remove a lot of unused and unnecessary code across module
boundaries.
Extend those parts of `circt-reduce` that interact with connect
operations and check for `ConnectOp` and `PartialConnectOp`, and make
them also check for `StrictConnectOp`.
Extend `circt-reducer` with some additional mechanism to appropriately
remove `firrtl.nla` ops when instances, modules, or ports are modified
or removed. Currently this is very FIRRTL-specific, but I hope to make
this more general-purpose in the future. With this fix the reducer
becomes more useful on FIRRTL inputs that make heavy use of non-local
annotations and non-local anchors, which is very likely if they use some
form of deduplication or proper multiple instantiation.
This initial commit handles building of the top-level hw.module when converting a handshake.func operation. All handshake modules are created as external hw modules. By doing so, follow-up commits may gradually implement each of the handshake operations using RTL dialect logic.
To transition from FIRRTL bundles with explicit ready/valid/data bundles, this commit relies on ESI channels for handshake module I/O as well as the top-level I/O.
Some changes to the flow are that:
- We're no longer inlining the handshake operations into the hw module. Instead, we maintain a value mapping from SSA values in the handshake.func to those in the hw.module, and maintain this using BackedgeBuilder operations. In general, an approach is taken of maintaining state outside the IR instead of inside the IR.
This is just the first commit in the process of transitioning away from FIRRTL for lowering Handshake operations; transitioning to be ESI based should hopefully also create a good basis for composing Handshake circuits with other parts of future HLS and CIRCT infrastructure.
Change end-to-end FIRRTL compilation behavior to preserve (via tapping) all
nodes and wires which are "named". A "named" node or wire is one whose name
does not begin with an underscore. Tapping is done by creating a "shadow node"
that is assigned the value of the actual wire and marked "don't touch".
This is done to enable better debug-ability of Chisel designs by enabling users
to always have references to named things they define in Chisel. More
specifically, anytime a Chisel user defines a `val foo = <expression>`, CIRCT
will now produce a wire called "foo" in the output Verilog.
Add a parser option for controlling whether or not "named" wires and
nodes will be preserved from FIRRTL to Verilog.
Add a firtool command-line option for disabling name preservation during
FIRRTL parsing.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This commit implements MergeConnectionPass to merge expanded connections into one connection.
LowerTypes fully expands aggregate connections even when semantically
we don't have to expand because it is necessary for ExpandWhen.
More specifically this pass folds the following patterns:
```
%dest(0) <= subfield %a(0)
%dest(1) <= subfield %a(1)
...
%dest(n) <= subfield %a(n)
```
into
```
%dest <= %a
```
This pass also merge connections if their source values are known to be
constant. If `aggressive-merging` flag is true, we will merge all connections
even when source values are not simplified.
This commit adds RemoveUnusedPortsPass to reduction passes and replaces
PortPruner with RemoveUnusedPortsPass. RemoveUnusedPortsPass would be
more powerfull since it prunus ports interprocedurally.
This commit adds RemoveUnusedPortsPass to prune unused ports.
RemoveUnusedPortsPass removes unused ports from the bottom of the
instance graph so that we can remove ports optimally. Ports are
not removed if they have annotations or inner sym.
This adds a pass to wire the "test_en" port of all modules named
EICG_Wrapper to a signal marked by the "DFTEnable" annotation. This is
used to support the Design For Testing clock gating.
* mlir::Identifier deprecated
* StringAttr::get(string, context) deprecated
* Many api changes in std dialect e.g. op.res() ==> op.getRes()
* getAsmBlockArgumentNames is moved to interface (https://reviews.llvm.org/D116018)
* populateFuncOpTypeConversionPattern =>
populateFunctionLikeOpTypeConversionPattern
* SmallVector::set_size() becomes private (https://reviews.llvm.org/D115380) replaced with resize()
* #dialect.mnemonic is elided by default https://reviews.llvm.org/D113873. For now, migrate by marking every type directive in asmFormat as qualified(https://reviews.llvm.org/D116905).
* Indices of LLVM::GEPOp are now required to be constant (https://reviews.llvm.org/D116759)
This commit adds preservePublicTypes option to preserve port types of
top-level and exeternal modules.
In chisel, external modules and top-level modules are implicitly assumed to have
lowered types. Therefore even in the aggregate presevartion mode, we
can't preserve them.
Add a FIRRTL pass to merge the read and write ports of a memory, if their
enable condition is mutually exclusive.
This is an implementation of the Scala InferReadWrite pass,
`passes/memlib/InferReadWrite.scala`.
The heuristic used to infer mutually exclusive conditions,
1. First constructs the And expression tree for both the read and write
enable conditions.
2. The conditions are mutually exclusive if any of the product terms is a
complement of each other.
3. Also check if both the ports are connected to the same clock.
This pass only looks for Seq memories, that is memory with read and write
latency of 1, and exactly two ports.
Some canonicalizers create new sv.if ops. As a result,
we get redundant if statement in output verilog.
This commit fixes the issue by moving HWCleanup to the later.
* [reduce] Add `ConnectSourceOperandForwarder` reduction
This commit adds a new reducion called `ConnectSourceOperandForwarder`.
If a wire is used only once as a destination of a connect, we can
forward the wire to one of operands of the source value.
For example, consider the following IR.
```mlir
%a = firrtl.wire : !firrtl.uint<1>
%src0 = firrtl.wire : !firrtl.uint<2>
%src1 = firrtl.bits %src0 0 to 0 : (!firrtl.uint<2>) -> !firrtl.uint<1>
firrtl.connect %a, %src1
```
ConnectSourceOperandForwarder reduces the IR above into
```mlir
%a = firrtl.wire : !firrtl.uint<2>
%src0 = firrtl.wire : !firrtl.uint<2>
firrtl.connect %a, %src0
```
This reduction is potentially useful for cleaning up chains of bits/pad
op inserted by the reducer.
Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>
This commit adds `preserve-aggregate` flag to enable experimental
feature to preserve passive aggregate wires/register/connection.
Currently, if preserve-aggregate flag is enabled, we change the
behavior of `peelTypes` function. We don't preserve aggregate if any
of the following condition holds:
1. They are ports of MemOp (Ports of MemOp must be ground types)
2. They are non-passive types
3. They contain an analog type
4. They are types with zero width.
This dialect is going to contain the CHIRRTL operations and types
currently in the FIRRTL dialect. This will provide better structuring
in the MLIR types as we don't want CHIRRTL types to be FIRRTL types.
For more information see this issue here:
https://github.com/llvm/circt/pull/2134
Add a new pass, RemoveResets, that replaces RegResetOps that have
invalidated initialization values with RegOps. This is part of a series
of patches that are intended to align CIRCT with the Scala FIRRTL
Compiler (SFC) interpretation of invalid. Previously, CIRCT relies on
canonicalization/folding of invalid values to do this optimization.
This pass enables future canonicalization/folding of invalid values to
zero (as the SFC does) without having to worry about performing this
optimization.
Run the RemoveResets pass as part of firtool after ExpandWhens and
before the first canonicalization. This enables conversion of
invalidated RegResetOps to RegOps before canonicalization (eventually)
interprets invalid values as zero.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This change adds an option to ignore the memory read enable signal during
memory lowering to register banks.
According to the FIRRTL spec, the read output is undefined if the read
enable signal is disabled.
But the `firrtl` implementation ignores the read enable signal on latency 0.
This change ensures that, in `HWMemSimImpl` by default the read output is set
to `X` if read enable is disabled, but if `ignore-read-enable-mem` option
is passed, then the read output is set with the data at the read address,
irrespective of the enable signal.
This provides an option to match the Scala FIRRTL compiler behavior.
John Demme