mirror of https://github.com/llvm/circt.git
[HandshakeToHW] Initial commit for handshake-to-hw (#2680)
This initial commit handles building of the top-level hw.module when converting a handshake.func operation. All handshake modules are created as external hw modules. By doing so, follow-up commits may gradually implement each of the handshake operations using RTL dialect logic. To transition from FIRRTL bundles with explicit ready/valid/data bundles, this commit relies on ESI channels for handshake module I/O as well as the top-level I/O. Some changes to the flow are that: - We're no longer inlining the handshake operations into the hw module. Instead, we maintain a value mapping from SSA values in the handshake.func to those in the hw.module, and maintain this using BackedgeBuilder operations. In general, an approach is taken of maintaining state outside the IR instead of inside the IR. This is just the first commit in the process of transitioning away from FIRRTL for lowering Handshake operations; transitioning to be ESI based should hopefully also create a good basis for composing Handshake circuits with other parts of future HLS and CIRCT infrastructure.
This commit is contained in:
Morten Borup Petersen
GitHub
parent
106815aea4
commit
c7c0765933
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@ -0,0 +1,27 @@
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//===- HandshakeToHW.h ------------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares passes which together will lower the Handshake dialect to
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// CIRCT RTL dialects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CIRCT_CONVERSION_HANDSHAKETOHW_H
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#define CIRCT_CONVERSION_HANDSHAKETOHW_H
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#include <memory>
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namespace mlir {
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class Pass;
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} // namespace mlir
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namespace circt {
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std::unique_ptr<mlir::Pass> createHandshakeToHWPass();
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} // namespace circt
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#endif // CIRCT_CONVERSION_HANDSHAKETOHW_H
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@ -19,6 +19,7 @@
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#include "circt/Conversion/FIRRTLToHW.h"
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#include "circt/Conversion/HWToLLHD.h"
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#include "circt/Conversion/HandshakeToFIRRTL.h"
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#include "circt/Conversion/HandshakeToHW.h"
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#include "circt/Conversion/LLHDToLLVM.h"
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#include "circt/Conversion/MooreToCore.h"
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#include "circt/Conversion/SCFToCalyx.h"
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@ -128,6 +128,19 @@ def LowerFIRRTLToHW : Pass<"lower-firrtl-to-hw", "mlir::ModuleOp"> {
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];
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}
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//===----------------------------------------------------------------------===//
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// HandshakeToHW
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//===----------------------------------------------------------------------===//
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def HandshakeToHW : Pass<"lower-handshake-to-hw", "mlir::ModuleOp"> {
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let summary = "Lower Handshake to ESI/HW/Comb/Seq";
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let description = [{
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Lower Handshake to ESI/HW/Comb/Seq.
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}];
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let constructor = "circt::createHandshakeToHWPass()";
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let dependentDialects = ["hw::HWDialect", "esi::ESIDialect"];
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}
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//===----------------------------------------------------------------------===//
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// HandshakeToFIRRTL
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//===----------------------------------------------------------------------===//
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@ -20,7 +20,8 @@ def FuncOp : Op<Handshake_Dialect, "func", [
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FunctionOpInterface,
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Symbol,
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RegionKindInterface,
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OpAsmOpInterface
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OpAsmOpInterface,
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HasClock
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]> {
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let summary = "Handshake dialect function.";
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let description = [{
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@ -4,6 +4,7 @@ add_subdirectory(ExportVerilog)
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add_subdirectory(FIRRTLToHW)
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add_subdirectory(HWToLLHD)
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add_subdirectory(HandshakeToFIRRTL)
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add_subdirectory(HandshakeToHW)
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add_subdirectory(LLHDToLLVM)
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add_subdirectory(MooreToCore)
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add_subdirectory(SCFToCalyx)
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@ -0,0 +1,19 @@
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add_circt_library(CIRCTHandshakeToHW
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HandshakeToHW.cpp
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ADDITIONAL_HEADER_DIRS
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${MLIR_MAIN_INCLUDE_DIR}/mlir/Conversion/HandshakeToHW
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LINK_LIBS PUBLIC
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CIRCTHW
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CIRCTESI
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CIRCTHandshake
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CIRCTHandshakeTransforms
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MLIRIR
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MLIRPass
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MLIRArithmetic
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MLIRControlFlow
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MLIRStandard
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MLIRSupport
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MLIRTransforms
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)
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@ -0,0 +1,603 @@
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//===- HandshakeToHW.cpp - Translate Handshake into HW ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//===----------------------------------------------------------------------===//
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//
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// This is the main Handshake to HW Conversion Pass Implementation.
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//
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//===----------------------------------------------------------------------===//
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#include "circt/Conversion/HandshakeToHW.h"
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#include "../PassDetail.h"
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#include "circt/Dialect/ESI/ESIOps.h"
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#include "circt/Dialect/HW/HWOps.h"
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#include "circt/Dialect/HW/HWTypes.h"
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#include "circt/Dialect/Handshake/HandshakeOps.h"
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#include "circt/Dialect/Handshake/HandshakePasses.h"
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#include "circt/Dialect/Handshake/Visitor.h"
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#include "circt/Support/BackedgeBuilder.h"
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#include "mlir/Dialect/MemRef/IR/MemRef.h"
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#include "mlir/IR/ImplicitLocOpBuilder.h"
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#include "mlir/Pass/PassManager.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "llvm/ADT/TypeSwitch.h"
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#include "llvm/Support/MathExtras.h"
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#include <variant>
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using namespace mlir;
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using namespace circt;
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using namespace circt::handshake;
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using namespace circt::hw;
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using NameUniquer = std::function<std::string(Operation *)>;
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/// Returns a submodule name resulting from an operation, without discriminating
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/// type information.
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static std::string getBareSubModuleName(Operation *oldOp) {
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// The dialect name is separated from the operation name by '.', which is not
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// valid in SystemVerilog module names. In case this name is used in
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// SystemVerilog output, replace '.' with '_'.
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std::string subModuleName = oldOp->getName().getStringRef().str();
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std::replace(subModuleName.begin(), subModuleName.end(), '.', '_');
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return subModuleName;
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}
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static std::string getCallName(Operation *op) {
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auto callOp = dyn_cast<handshake::InstanceOp>(op);
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return callOp ? callOp.getModule().str() : getBareSubModuleName(op);
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}
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/// Extracts the type of the data-carrying type of opType. If opType is an ESI
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/// channel, getHandshakeBundleDataType extracts the data-carrying type, else,
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/// assume that opType itself is the data-carrying type.
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static Type getOperandDataType(Value op) {
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auto opType = op.getType();
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if (auto channelType = opType.dyn_cast<esi::ChannelPort>())
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return channelType.getInner();
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return opType;
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}
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/// Filters NoneType's from the input.
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static SmallVector<Type> filterNoneTypes(ArrayRef<Type> input) {
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SmallVector<Type> filterRes;
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llvm::copy_if(input, std::back_inserter(filterRes),
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[](Type type) { return !type.isa<NoneType>(); });
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return filterRes;
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}
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/// Returns a set of types which may uniquely identify the provided op. Return
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/// value is <inputTypes, outputTypes>.
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using DiscriminatingTypes = std::pair<SmallVector<Type>, SmallVector<Type>>;
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static DiscriminatingTypes getHandshakeDiscriminatingTypes(Operation *op) {
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return TypeSwitch<Operation *, DiscriminatingTypes>(op)
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.Case<MemoryOp>([&](auto memOp) {
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return DiscriminatingTypes{{}, {memOp.memRefType().getElementType()}};
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})
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.Default([&](auto) {
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// By default, all in- and output types which is not a control type
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// (NoneType) are discriminating types.
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std::vector<Type> inTypes, outTypes;
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llvm::transform(op->getOperands(), std::back_inserter(inTypes),
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getOperandDataType);
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llvm::transform(op->getResults(), std::back_inserter(outTypes),
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getOperandDataType);
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return DiscriminatingTypes{filterNoneTypes(inTypes),
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filterNoneTypes(outTypes)};
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});
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}
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// Wraps a type into an ESI ChannelPort type. The inner type is converted to
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// ensure comprehensability by the RTL dialects.
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static Type esiWrapper(Type t) {
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// Translate none- and index types to something HW understands.
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if (t.isa<NoneType>())
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t = IntegerType::get(t.getContext(), 0);
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else if (t.isa<IndexType>())
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t = IntegerType::get(t.getContext(), 64);
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return esi::ChannelPort::get(t.getContext(), t);
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};
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/// Get type name. Currently we only support integer or index types.
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/// The emitted type aligns with the getFIRRTLType() method. Thus all integers
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/// other than signed integers will be emitted as unsigned.
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static std::string getTypeName(Location loc, Type type) {
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std::string typeName;
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// Builtin types
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if (type.isIntOrIndex()) {
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if (auto indexType = type.dyn_cast<IndexType>())
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typeName += "_ui" + std::to_string(indexType.kInternalStorageBitWidth);
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else if (type.isSignedInteger())
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typeName += "_si" + std::to_string(type.getIntOrFloatBitWidth());
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else
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typeName += "_ui" + std::to_string(type.getIntOrFloatBitWidth());
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} else
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emitError(loc) << "unsupported data type '" << type << "'";
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return typeName;
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}
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/// A class to be used with getPortInfoForOp. Provides an opaque interface for
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/// generating the port names of an operation; handshake operations generate
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/// names by the Handshake NamedIOInterface; and other operations, such as
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/// arith ops, are assigned default names.
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class HandshakePortNameGenerator {
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public:
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explicit HandshakePortNameGenerator(Operation *op)
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: builder(op->getContext()) {
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auto namedOpInterface = dyn_cast<handshake::NamedIOInterface>(op);
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if (namedOpInterface)
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inferFromNamedOpInterface(namedOpInterface);
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else if (auto funcOp = dyn_cast<handshake::FuncOp>(op))
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inferFromFuncOp(funcOp);
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else
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inferDefault(op);
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}
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StringAttr inputName(unsigned idx) { return inputs[idx]; }
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StringAttr outputName(unsigned idx) { return outputs[idx]; }
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private:
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using IdxToStrF = const std::function<std::string(unsigned)> &;
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void infer(Operation *op, IdxToStrF &inF, IdxToStrF &outF) {
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llvm::transform(
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llvm::enumerate(op->getOperandTypes()), std::back_inserter(inputs),
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[&](auto it) { return builder.getStringAttr(inF(it.index())); });
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llvm::transform(
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llvm::enumerate(op->getResultTypes()), std::back_inserter(outputs),
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[&](auto it) { return builder.getStringAttr(outF(it.index())); });
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}
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void inferDefault(Operation *op) {
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infer(
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op, [](unsigned idx) { return "in" + std::to_string(idx); },
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[](unsigned idx) { return "out" + std::to_string(idx); });
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}
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void inferFromNamedOpInterface(handshake::NamedIOInterface op) {
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infer(
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op, [&](unsigned idx) { return op.getOperandName(idx); },
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[&](unsigned idx) { return op.getResultName(idx); });
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}
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void inferFromFuncOp(handshake::FuncOp op) {
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auto inF = [&](unsigned idx) { return op.getArgName(idx).str(); };
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auto outF = [&](unsigned idx) { return op.getResName(idx).str(); };
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llvm::transform(
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llvm::enumerate(op.getType().getInputs()), std::back_inserter(inputs),
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[&](auto it) { return builder.getStringAttr(inF(it.index())); });
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llvm::transform(
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llvm::enumerate(op.getType().getResults()), std::back_inserter(outputs),
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[&](auto it) { return builder.getStringAttr(outF(it.index())); });
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}
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Builder builder;
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llvm::SmallVector<StringAttr> inputs;
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llvm::SmallVector<StringAttr> outputs;
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};
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/// Construct a name for creating HW sub-module.
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static std::string getSubModuleName(Operation *oldOp) {
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if (auto instanceOp = dyn_cast<handshake::InstanceOp>(oldOp); instanceOp)
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return instanceOp.getModule().str();
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std::string subModuleName = getBareSubModuleName(oldOp);
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// Add value of the constant operation.
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if (auto constOp = dyn_cast<handshake::ConstantOp>(oldOp)) {
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if (auto intAttr = constOp.getValue().dyn_cast<IntegerAttr>()) {
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auto intType = intAttr.getType();
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if (intType.isSignedInteger())
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subModuleName += "_c" + std::to_string(intAttr.getSInt());
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else if (intType.isUnsignedInteger())
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subModuleName += "_c" + std::to_string(intAttr.getUInt());
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else
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subModuleName += "_c" + std::to_string((uint64_t)intAttr.getInt());
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} else
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oldOp->emitError("unsupported constant type");
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}
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// Add discriminating in- and output types.
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auto [inTypes, outTypes] = getHandshakeDiscriminatingTypes(oldOp);
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if (!inTypes.empty())
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subModuleName += "_in";
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for (auto inType : inTypes)
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subModuleName += getTypeName(oldOp->getLoc(), inType);
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if (!outTypes.empty())
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subModuleName += "_out";
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for (auto outType : outTypes)
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subModuleName += getTypeName(oldOp->getLoc(), outType);
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// Add memory ID.
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if (auto memOp = dyn_cast<handshake::MemoryOp>(oldOp))
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subModuleName += "_id" + std::to_string(memOp.id());
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// Add compare kind.
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if (auto comOp = dyn_cast<mlir::arith::CmpIOp>(oldOp))
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subModuleName += "_" + stringifyEnum(comOp.getPredicate()).str();
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// Add buffer information.
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if (auto bufferOp = dyn_cast<handshake::BufferOp>(oldOp)) {
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subModuleName += "_" + std::to_string(bufferOp.getNumSlots()) + "slots";
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if (bufferOp.isSequential())
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subModuleName += "_seq";
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else
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subModuleName += "_fifo";
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}
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// Add control information.
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if (auto ctrlInterface = dyn_cast<handshake::ControlInterface>(oldOp);
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ctrlInterface && ctrlInterface.isControl()) {
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// Add some additional discriminating info for non-typed operations.
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subModuleName += "_" + std::to_string(oldOp->getNumOperands()) + "ins_" +
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std::to_string(oldOp->getNumResults()) + "outs";
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subModuleName += "_ctrl";
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} else {
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assert(
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(!inTypes.empty() || !outTypes.empty()) &&
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"Insufficient discriminating type info generated for the operation!");
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}
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return subModuleName;
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}
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//===----------------------------------------------------------------------===//
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// HW Sub-module Related Functions
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//===----------------------------------------------------------------------===//
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/// Check whether a submodule with the same name has been created elsewhere in
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/// the top level module. Return the matched module operation if true, otherwise
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/// return nullptr.
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static Operation *checkSubModuleOp(mlir::ModuleOp parentModule,
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StringRef modName) {
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if (auto mod = parentModule.lookupSymbol<HWModuleOp>(modName))
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return mod;
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if (auto mod = parentModule.lookupSymbol<HWModuleExternOp>(modName))
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return mod;
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return nullptr;
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}
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static Operation *checkSubModuleOp(mlir::ModuleOp parentModule,
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Operation *oldOp) {
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auto *moduleOp = checkSubModuleOp(parentModule, getSubModuleName(oldOp));
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if (isa<handshake::InstanceOp>(oldOp))
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assert(moduleOp &&
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"handshake.instance target modules should always have been lowered "
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"before the modules that reference them!");
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return moduleOp;
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}
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static llvm::SmallVector<PortInfo>
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getPortInfoForOp(ConversionPatternRewriter &rewriter, Operation *op,
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TypeRange inputs, TypeRange outputs) {
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llvm::SmallVector<PortInfo> ports;
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HandshakePortNameGenerator portNames(op);
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// Add all inputs of funcOp.
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unsigned inIdx = 0;
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for (auto &arg : llvm::enumerate(inputs)) {
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ports.push_back({portNames.inputName(arg.index()), PortDirection::INPUT,
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esiWrapper(arg.value()), arg.index(), StringAttr{}});
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inIdx++;
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}
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// Add all outputs of funcOp.
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for (auto &res : llvm::enumerate(outputs)) {
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ports.push_back({portNames.outputName(res.index()), PortDirection::OUTPUT,
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esiWrapper(res.value()), res.index(), StringAttr{}});
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}
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// Add clock and reset signals.
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if (op->hasTrait<mlir::OpTrait::HasClock>()) {
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ports.push_back({rewriter.getStringAttr("clock"), PortDirection::INPUT,
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rewriter.getI1Type(), inIdx++, StringAttr{}});
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ports.push_back({rewriter.getStringAttr("reset"), PortDirection::INPUT,
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rewriter.getI1Type(), inIdx, StringAttr{}});
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}
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return ports;
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}
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/// Returns a vector of PortInfo's which defines the FIRRTL interface of the
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/// to-be-converted op.
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static llvm::SmallVector<PortInfo>
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getPortInfoForOp(ConversionPatternRewriter &rewriter, Operation *op) {
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return getPortInfoForOp(rewriter, op, op->getOperandTypes(),
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op->getResultTypes());
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}
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/// All standard expressions and handshake elastic components will be converted
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/// to a HW sub-module and be instantiated in the top-module.
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static HWModuleExternOp createSubModuleOp(ModuleOp parentModule,
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Operation *oldOp,
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ConversionPatternRewriter &rewriter) {
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OpBuilder::InsertionGuard g(rewriter);
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rewriter.setInsertionPointToStart(parentModule.getBody());
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auto ports = getPortInfoForOp(rewriter, oldOp);
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// todo: HWModuleOp; for this initial commit we'll leave this as an extern op.
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return rewriter.create<HWModuleExternOp>(
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parentModule.getLoc(), rewriter.getStringAttr(getSubModuleName(oldOp)),
|
||||
ports);
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// HW Top-module Related Functions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
static hw::HWModuleOp createTopModuleOp(handshake::FuncOp funcOp,
|
||||
ConversionPatternRewriter &rewriter) {
|
||||
llvm::SmallVector<PortInfo, 8> ports =
|
||||
getPortInfoForOp(rewriter, funcOp, funcOp.getType().getInputs(),
|
||||
funcOp.getType().getResults());
|
||||
|
||||
// Create a HW module.
|
||||
auto hwModuleOp = rewriter.create<hw::HWModuleOp>(
|
||||
funcOp.getLoc(), rewriter.getStringAttr(funcOp.getName()), ports);
|
||||
|
||||
// Remove the default created hw_output operation.
|
||||
auto outputOps = hwModuleOp.getOps<hw::OutputOp>();
|
||||
assert(std::distance(outputOps.begin(), outputOps.end()) == 1 &&
|
||||
"Expected exactly 1 default created hw_output operation");
|
||||
rewriter.eraseOp(*outputOps.begin());
|
||||
|
||||
return hwModuleOp;
|
||||
}
|
||||
|
||||
static bool isMemrefType(Type t) { return t.isa<mlir::MemRefType>(); }
|
||||
static LogicalResult verifyHandshakeFuncOp(handshake::FuncOp &funcOp) {
|
||||
// @TODO: memory I/O is not yet supported. Figure out how to support memory
|
||||
// services in ESI.
|
||||
if (llvm::any_of(funcOp.getArgumentTypes(), isMemrefType) ||
|
||||
llvm::any_of(funcOp.getResultTypes(), isMemrefType))
|
||||
return emitError(funcOp.getLoc())
|
||||
<< "memref ports are not yet supported in handshake-to-hw lowering.";
|
||||
return success();
|
||||
}
|
||||
|
||||
namespace {
|
||||
|
||||
using TypeTransformer = llvm::function_ref<Type(Type)>;
|
||||
static Type defaultTypeTransformer(Type t) { return t; }
|
||||
|
||||
/// The ValueMapping class facilitates the definition and connection of SSA
|
||||
/// def-use chains between two separate regions - a 'from' region (defining
|
||||
/// use-def chains) and a 'to' region (where new operations are created based on
|
||||
/// the 'from' region).´
|
||||
class ValueMapping {
|
||||
public:
|
||||
explicit ValueMapping(BackedgeBuilder &bb) : bb(bb) {}
|
||||
|
||||
// Get the mapped value of value 'from'. If no mapping has been registered, a
|
||||
// new backedge is created. The type of the mapped value may optionally be
|
||||
// modified through the 'typeTransformer'.
|
||||
Value get(Value from,
|
||||
TypeTransformer typeTransformer = defaultTypeTransformer) {
|
||||
if (mapping.count(from) == 0) {
|
||||
// Create a backedge which will be resolved at a later time once all
|
||||
// operands are created.
|
||||
mapping[from] = bb.get(typeTransformer(from.getType()));
|
||||
}
|
||||
auto operandMapping = mapping[from];
|
||||
Value mappedOperand;
|
||||
if (auto *v = std::get_if<Value>(&operandMapping))
|
||||
mappedOperand = *v;
|
||||
else
|
||||
mappedOperand = std::get<Backedge>(operandMapping);
|
||||
return mappedOperand;
|
||||
}
|
||||
|
||||
llvm::SmallVector<Value>
|
||||
get(ValueRange from,
|
||||
TypeTransformer typeTransformer = defaultTypeTransformer) {
|
||||
llvm::SmallVector<Value> to;
|
||||
for (auto f : from)
|
||||
to.push_back(get(f, typeTransformer));
|
||||
return to;
|
||||
}
|
||||
|
||||
// Set the mapped value of 'from' to 'to'. If 'from' is already mapped to a
|
||||
// backedge, replaces that backedge with 'to'.
|
||||
void set(Value from, Value to) {
|
||||
auto it = mapping.find(from);
|
||||
if (it != mapping.end()) {
|
||||
if (auto *backedge = std::get_if<Backedge>(&it->second)) {
|
||||
backedge->setValue(to);
|
||||
} else {
|
||||
assert(false && "'from' was already mapped to a final value!");
|
||||
}
|
||||
}
|
||||
// Register the new mapping
|
||||
mapping[from] = to;
|
||||
}
|
||||
|
||||
void set(ValueRange from, ValueRange to) {
|
||||
assert(from.size() == to.size() &&
|
||||
"Expected # of 'from' values and # of 'to' values to be identical.");
|
||||
for (auto [f, t] : llvm::zip(from, to))
|
||||
set(f, t);
|
||||
}
|
||||
|
||||
private:
|
||||
BackedgeBuilder &bb;
|
||||
DenseMap<Value, std::variant<Value, Backedge>> mapping;
|
||||
};
|
||||
|
||||
// Shared state used by various functions; captured in a struct to reduce the
|
||||
// number of arguments that we have to pass around.
|
||||
struct HandshakeLoweringState {
|
||||
ValueMapping &mapping;
|
||||
ModuleOp parentModule;
|
||||
hw::HWModuleOp hwModuleOp;
|
||||
NameUniquer nameUniquer;
|
||||
Value clock;
|
||||
Value reset;
|
||||
};
|
||||
|
||||
static Operation *createOpInHWModule(ConversionPatternRewriter &rewriter,
|
||||
HandshakeLoweringState &ls,
|
||||
Operation *op) {
|
||||
OpBuilder::InsertionGuard g(rewriter);
|
||||
rewriter.setInsertionPointToEnd(ls.hwModuleOp.getBodyBlock());
|
||||
|
||||
// Create a mapping between the operands of 'op' and the replacement operands
|
||||
// in the target hwModule. For any missing operands, we create a new backedge.
|
||||
llvm::SmallVector<Value> hwOperands =
|
||||
ls.mapping.get(op->getOperands(), esiWrapper);
|
||||
|
||||
// Add clock and reset if needed.
|
||||
if (op->hasTrait<mlir::OpTrait::HasClock>())
|
||||
hwOperands.append({ls.clock, ls.reset});
|
||||
|
||||
// Check if a sub-module for the operation already exists.
|
||||
Operation *subModuleSymOp = checkSubModuleOp(ls.parentModule, op);
|
||||
if (!subModuleSymOp) {
|
||||
subModuleSymOp = createSubModuleOp(ls.parentModule, op, rewriter);
|
||||
// TODO: fill the subModuleSymOp with the meat of the handshake
|
||||
// operations.
|
||||
}
|
||||
|
||||
// Instantiate the new created sub-module.
|
||||
rewriter.setInsertionPointToEnd(ls.hwModuleOp.getBodyBlock());
|
||||
auto submoduleInstanceOp = rewriter.create<hw::InstanceOp>(
|
||||
op->getLoc(), subModuleSymOp, rewriter.getStringAttr(ls.nameUniquer(op)),
|
||||
hwOperands);
|
||||
|
||||
// Resolve any previously created backedges that referred to the results of
|
||||
// 'op'.
|
||||
ls.mapping.set(op->getResults(), submoduleInstanceOp.getResults());
|
||||
|
||||
return submoduleInstanceOp;
|
||||
}
|
||||
|
||||
static void convertReturnOp(handshake::ReturnOp op, HandshakeLoweringState &ls,
|
||||
ConversionPatternRewriter &rewriter) {
|
||||
OpBuilder::InsertionGuard g(rewriter);
|
||||
rewriter.setInsertionPointToEnd(ls.hwModuleOp.getBodyBlock());
|
||||
rewriter.create<hw::OutputOp>(op.getLoc(), ls.mapping.get(op.getOperands()));
|
||||
}
|
||||
|
||||
struct HandshakeFuncOpLowering : public OpConversionPattern<handshake::FuncOp> {
|
||||
using OpConversionPattern<handshake::FuncOp>::OpConversionPattern;
|
||||
HandshakeFuncOpLowering(MLIRContext *context)
|
||||
: OpConversionPattern<handshake::FuncOp>(context) {}
|
||||
|
||||
LogicalResult
|
||||
matchAndRewrite(handshake::FuncOp funcOp, OpAdaptor adaptor,
|
||||
ConversionPatternRewriter &rewriter) const override {
|
||||
if (failed(verifyHandshakeFuncOp(funcOp)))
|
||||
return failure();
|
||||
|
||||
ModuleOp parentModule = funcOp->getParentOfType<ModuleOp>();
|
||||
rewriter.setInsertionPointToStart(funcOp->getBlock());
|
||||
HWModuleOp topModuleOp = createTopModuleOp(funcOp, rewriter);
|
||||
Value clockPort =
|
||||
topModuleOp.getArgument(topModuleOp.getNumArguments() - 2);
|
||||
Value resetPort =
|
||||
topModuleOp.getArgument(topModuleOp.getNumArguments() - 1);
|
||||
|
||||
// Create a uniquer function for creating instance names.
|
||||
NameUniquer instanceUniquer = [&](Operation *op) {
|
||||
std::string instName = getCallName(op);
|
||||
if (auto idAttr = op->getAttrOfType<IntegerAttr>("handshake_id");
|
||||
idAttr) {
|
||||
// We use a special naming convention for operations which have a
|
||||
// 'handshake_id' attribute.
|
||||
instName += "_id" + std::to_string(idAttr.getValue().getZExtValue());
|
||||
} else {
|
||||
// Fallback to just prefixing with an integer.
|
||||
instName += std::to_string(instanceNameCntr[instName]++);
|
||||
}
|
||||
return instName;
|
||||
};
|
||||
|
||||
// Initialize the Handshake lowering state.
|
||||
BackedgeBuilder bb(rewriter, funcOp.getLoc());
|
||||
ValueMapping valueMapping(bb);
|
||||
auto ls = HandshakeLoweringState{valueMapping, parentModule, topModuleOp,
|
||||
instanceUniquer, clockPort, resetPort};
|
||||
|
||||
// Extend value mapping with input arguments. Drop the 2 last inputs from
|
||||
// the HW module (clock and reset).
|
||||
valueMapping.set(funcOp.getArguments(),
|
||||
topModuleOp.getArguments().drop_back(2));
|
||||
|
||||
// Traverse and convert each operation in funcOp.
|
||||
for (Operation &op : funcOp.front()) {
|
||||
if (isa<hw::OutputOp>(op)) {
|
||||
// Skip the default created HWModule terminator, for now.
|
||||
continue;
|
||||
}
|
||||
if (auto returnOp = dyn_cast<handshake::ReturnOp>(op)) {
|
||||
convertReturnOp(returnOp, ls, rewriter);
|
||||
} else {
|
||||
// Regular operation.
|
||||
createOpInHWModule(rewriter, ls, &op);
|
||||
}
|
||||
}
|
||||
rewriter.eraseOp(funcOp);
|
||||
return success();
|
||||
}
|
||||
|
||||
private:
|
||||
/// Maintain a map from module names to the # of times the module has been
|
||||
/// instantiated inside this module. This is used to generate unique names for
|
||||
/// each instance.
|
||||
mutable std::map<std::string, unsigned> instanceNameCntr;
|
||||
};
|
||||
|
||||
class HandshakeToHWPass : public HandshakeToHWBase<HandshakeToHWPass> {
|
||||
public:
|
||||
void runOnOperation() override {
|
||||
auto op = getOperation();
|
||||
|
||||
// Lowering to HW requires that every value is used exactly once. Check
|
||||
// whether this precondition is met, and if not, exit.
|
||||
if (llvm::any_of(op.getOps<handshake::FuncOp>(), [](auto f) {
|
||||
return failed(verifyAllValuesHasOneUse(f));
|
||||
})) {
|
||||
signalPassFailure();
|
||||
return;
|
||||
}
|
||||
|
||||
// Resolve the instance graph to get a top-level module.
|
||||
std::string topLevel;
|
||||
handshake::InstanceGraph uses;
|
||||
SmallVector<std::string> sortedFuncs;
|
||||
if (resolveInstanceGraph(op, uses, topLevel, sortedFuncs).failed()) {
|
||||
signalPassFailure();
|
||||
return;
|
||||
}
|
||||
|
||||
ConversionTarget target(getContext());
|
||||
target.addLegalDialect<HWDialect>();
|
||||
target.addIllegalDialect<handshake::HandshakeDialect>();
|
||||
|
||||
// Convert the handshake.func operations in post-order wrt. the instance
|
||||
// graph. This ensures that any referenced submodules (through
|
||||
// handshake.instance) has already been lowered, and their HW module
|
||||
// equivalents are available.
|
||||
for (auto &funcName : llvm::reverse(sortedFuncs)) {
|
||||
RewritePatternSet patterns(op.getContext());
|
||||
patterns.insert<HandshakeFuncOpLowering>(op.getContext());
|
||||
auto *funcOp = op.lookupSymbol(funcName);
|
||||
assert(funcOp && "Symbol not found in module!");
|
||||
if (failed(applyPartialConversion(funcOp, target, std::move(patterns)))) {
|
||||
signalPassFailure();
|
||||
funcOp->emitOpError() << "error during conversion";
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
} // end anonymous namespace
|
||||
|
||||
std::unique_ptr<mlir::Pass> circt::createHandshakeToHWPass() {
|
||||
return std::make_unique<HandshakeToHWPass>();
|
||||
}
|
||||
|
|
@ -52,6 +52,10 @@ class HandshakeDialect;
|
|||
class FuncOp;
|
||||
} // namespace handshake
|
||||
|
||||
namespace esi {
|
||||
class ESIDialect;
|
||||
} // namespace esi
|
||||
|
||||
namespace moore {
|
||||
class MooreDialect;
|
||||
} // namespace moore
|
||||
|
|
|
|||
|
|
@ -0,0 +1,73 @@
|
|||
// RUN: circt-opt -lower-handshake-to-hw -split-input-file %s | FileCheck %s
|
||||
|
||||
// CHECK-LABEL: hw.module.extern @arith_addi_in_ui64_ui64_out_ui64(
|
||||
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i64>,
|
||||
// CHECK-SAME: %[[VAL_1:.*]]: !esi.channel<i64>) -> (out0: !esi.channel<i64>)
|
||||
// CHECK: hw.module.extern @handshake_cond_br_in_ui1_2ins_2outs_ctrl(%[[VAL_2:.*]]: !esi.channel<i1>, %[[VAL_3:.*]]: !esi.channel<i0>) -> (outTrue: !esi.channel<i0>, outFalse: !esi.channel<i0>)
|
||||
// CHECK: hw.module.extern @handshake_sink_in_ui64(%[[VAL_0]]: !esi.channel<i64>)
|
||||
// CHECK: hw.module.extern @handshake_cond_br_in_ui1_ui64_out_ui64_ui64(%[[VAL_2]]: !esi.channel<i1>, %[[VAL_3]]: !esi.channel<i64>) -> (outTrue: !esi.channel<i64>, outFalse: !esi.channel<i64>)
|
||||
// CHECK: hw.module.extern @handshake_fork_in_ui1_out_ui1_ui1_ui1_ui1_ui1(%[[VAL_0]]: !esi.channel<i1>, %[[VAL_4:.*]]: i1, %[[VAL_5:.*]]: i1) -> (out0: !esi.channel<i1>, out1: !esi.channel<i1>, out2: !esi.channel<i1>, out3: !esi.channel<i1>, out4: !esi.channel<i1>)
|
||||
// CHECK: hw.module.extern @arith_cmpi_in_ui64_ui64_out_ui1_slt(%[[VAL_0]]: !esi.channel<i64>, %[[VAL_1]]: !esi.channel<i64>) -> (out0: !esi.channel<i1>)
|
||||
// CHECK: hw.module.extern @handshake_fork_in_ui64_out_ui64_ui64(%[[VAL_0]]: !esi.channel<i64>, %[[VAL_4]]: i1, %[[VAL_5]]: i1) -> (out0: !esi.channel<i64>, out1: !esi.channel<i64>)
|
||||
// CHECK: hw.module.extern @handshake_mux_in_ui1_ui64_ui64_out_ui64(%[[VAL_6:.*]]: !esi.channel<i1>, %[[VAL_0]]: !esi.channel<i64>, %[[VAL_1]]: !esi.channel<i64>) -> (out0: !esi.channel<i64>)
|
||||
// CHECK: hw.module.extern @handshake_mux_in_ui1_3ins_1outs_ctrl(%[[VAL_6]]: !esi.channel<i1>, %[[VAL_0]]: !esi.channel<i0>, %[[VAL_1]]: !esi.channel<i0>) -> (out0: !esi.channel<i0>)
|
||||
// CHECK: hw.module.extern @handshake_fork_in_ui1_out_ui1_ui1_ui1_ui1(%[[VAL_0]]: !esi.channel<i1>, %[[VAL_4]]: i1, %[[VAL_5]]: i1) -> (out0: !esi.channel<i1>, out1: !esi.channel<i1>, out2: !esi.channel<i1>, out3: !esi.channel<i1>)
|
||||
// CHECK: hw.module.extern @handshake_buffer_in_ui1_out_ui1_1slots_seq(%[[VAL_0]]: !esi.channel<i1>, %[[VAL_4]]: i1, %[[VAL_5]]: i1) -> (out0: !esi.channel<i1>)
|
||||
// CHECK: hw.module.extern @handshake_constant_c42_out_ui64(%[[VAL_7:.*]]: !esi.channel<i0>) -> (out0: !esi.channel<i64>)
|
||||
// CHECK: hw.module.extern @handshake_constant_c1_out_ui64(%[[VAL_7]]: !esi.channel<i0>) -> (out0: !esi.channel<i64>)
|
||||
// CHECK: hw.module.extern @handshake_fork_1ins_4outs_ctrl(%[[VAL_0]]: !esi.channel<i0>, %[[VAL_4]]: i1, %[[VAL_5]]: i1) -> (out0: !esi.channel<i0>, out1: !esi.channel<i0>, out2: !esi.channel<i0>, out3: !esi.channel<i0>)
|
||||
|
||||
// CHECK-LABEL: hw.module @main(
|
||||
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>,
|
||||
// CHECK-SAME: %[[VAL_4:.*]]: i1,
|
||||
// CHECK-SAME: %[[VAL_5:.*]]: i1) -> (out0: !esi.channel<i64>, outCtrl: !esi.channel<i0>) {
|
||||
// CHECK: %[[VAL_1:.*]], %[[VAL_2:.*]], %[[VAL_3:.*]], %[[VAL_42:.*]] = hw.instance "handshake_fork0" @handshake_fork_1ins_4outs_ctrl(in0: %[[VAL_0]]: !esi.channel<i0>, clock: %[[VAL_4]]: i1, reset: %[[VAL_5]]: i1) -> (out0: !esi.channel<i0>, out1: !esi.channel<i0>, out2: !esi.channel<i0>, out3: !esi.channel<i0>)
|
||||
// CHECK: %[[VAL_52:.*]] = hw.instance "handshake_constant0" @handshake_constant_c1_out_ui64(ctrl: %[[VAL_3]]: !esi.channel<i0>) -> (out0: !esi.channel<i64>)
|
||||
// CHECK: %[[VAL_6:.*]] = hw.instance "handshake_constant1" @handshake_constant_c42_out_ui64(ctrl: %[[VAL_2]]: !esi.channel<i0>) -> (out0: !esi.channel<i64>)
|
||||
// CHECK: %[[VAL_7:.*]] = hw.instance "handshake_constant2" @handshake_constant_c1_out_ui64(ctrl: %[[VAL_1]]: !esi.channel<i0>) -> (out0: !esi.channel<i64>)
|
||||
// CHECK: %[[VAL_8:.*]] = hw.instance "handshake_buffer0" @handshake_buffer_in_ui1_out_ui1_1slots_seq(in0: %[[VAL_9:.*]]: !esi.channel<i1>, clock: %[[VAL_4]]: i1, reset: %[[VAL_5]]: i1) -> (out0: !esi.channel<i1>)
|
||||
// CHECK: %[[VAL_10:.*]], %[[VAL_11:.*]], %[[VAL_12:.*]], %[[VAL_13:.*]] = hw.instance "handshake_fork1" @handshake_fork_in_ui1_out_ui1_ui1_ui1_ui1(in0: %[[VAL_8]]: !esi.channel<i1>, clock: %[[VAL_4]]: i1, reset: %[[VAL_5]]: i1) -> (out0: !esi.channel<i1>, out1: !esi.channel<i1>, out2: !esi.channel<i1>, out3: !esi.channel<i1>)
|
||||
// CHECK: %[[VAL_14:.*]] = hw.instance "handshake_mux0" @handshake_mux_in_ui1_3ins_1outs_ctrl(select: %[[VAL_13]]: !esi.channel<i1>, in0: %[[VAL_42]]: !esi.channel<i0>, in1: %[[VAL_15:.*]]: !esi.channel<i0>) -> (out0: !esi.channel<i0>)
|
||||
// CHECK: %[[VAL_16:.*]] = hw.instance "handshake_mux1" @handshake_mux_in_ui1_ui64_ui64_out_ui64(select: %[[VAL_12]]: !esi.channel<i1>, in0: %[[VAL_6]]: !esi.channel<i64>, in1: %[[VAL_17:.*]]: !esi.channel<i64>) -> (out0: !esi.channel<i64>)
|
||||
// CHECK: %[[VAL_18:.*]], %[[VAL_19:.*]] = hw.instance "handshake_fork2" @handshake_fork_in_ui64_out_ui64_ui64(in0: %[[VAL_16]]: !esi.channel<i64>, clock: %[[VAL_4]]: i1, reset: %[[VAL_5]]: i1) -> (out0: !esi.channel<i64>, out1: !esi.channel<i64>)
|
||||
// CHECK: %[[VAL_20:.*]] = hw.instance "handshake_mux2" @handshake_mux_in_ui1_ui64_ui64_out_ui64(select: %[[VAL_11]]: !esi.channel<i1>, in0: %[[VAL_7]]: !esi.channel<i64>, in1: %[[VAL_21:.*]]: !esi.channel<i64>) -> (out0: !esi.channel<i64>)
|
||||
// CHECK: %[[VAL_22:.*]] = hw.instance "handshake_mux3" @handshake_mux_in_ui1_ui64_ui64_out_ui64(select: %[[VAL_10]]: !esi.channel<i1>, in0: %[[VAL_52]]: !esi.channel<i64>, in1: %[[VAL_23:.*]]: !esi.channel<i64>) -> (out0: !esi.channel<i64>)
|
||||
// CHECK: %[[VAL_24:.*]], %[[VAL_25:.*]] = hw.instance "handshake_fork3" @handshake_fork_in_ui64_out_ui64_ui64(in0: %[[VAL_22]]: !esi.channel<i64>, clock: %[[VAL_4]]: i1, reset: %[[VAL_5]]: i1) -> (out0: !esi.channel<i64>, out1: !esi.channel<i64>)
|
||||
// CHECK: %[[VAL_26:.*]] = hw.instance "arith_cmpi0" @arith_cmpi_in_ui64_ui64_out_ui1_slt(in0: %[[VAL_24]]: !esi.channel<i64>, in1: %[[VAL_18]]: !esi.channel<i64>) -> (out0: !esi.channel<i1>)
|
||||
// CHECK: %[[VAL_9]], %[[VAL_27:.*]], %[[VAL_28:.*]], %[[VAL_29:.*]], %[[VAL_30:.*]] = hw.instance "handshake_fork4" @handshake_fork_in_ui1_out_ui1_ui1_ui1_ui1_ui1(in0: %[[VAL_26]]: !esi.channel<i1>, clock: %[[VAL_4]]: i1, reset: %[[VAL_5]]: i1) -> (out0: !esi.channel<i1>, out1: !esi.channel<i1>, out2: !esi.channel<i1>, out3: !esi.channel<i1>, out4: !esi.channel<i1>)
|
||||
// CHECK: %[[VAL_17]], %[[VAL_31:.*]] = hw.instance "handshake_cond_br0" @handshake_cond_br_in_ui1_ui64_out_ui64_ui64(cond: %[[VAL_30]]: !esi.channel<i1>, data: %[[VAL_19]]: !esi.channel<i64>) -> (outTrue: !esi.channel<i64>, outFalse: !esi.channel<i64>)
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||||
// CHECK: hw.instance "handshake_sink0" @handshake_sink_in_ui64(in0: %[[VAL_31]]: !esi.channel<i64>) -> ()
|
||||
// CHECK: %[[VAL_32:.*]], %[[VAL_33:.*]] = hw.instance "handshake_cond_br1" @handshake_cond_br_in_ui1_ui64_out_ui64_ui64(cond: %[[VAL_29]]: !esi.channel<i1>, data: %[[VAL_20]]: !esi.channel<i64>) -> (outTrue: !esi.channel<i64>, outFalse: !esi.channel<i64>)
|
||||
// CHECK: hw.instance "handshake_sink1" @handshake_sink_in_ui64(in0: %[[VAL_33]]: !esi.channel<i64>) -> ()
|
||||
// CHECK: %[[VAL_15]], %[[VAL_34:.*]] = hw.instance "handshake_cond_br2" @handshake_cond_br_in_ui1_2ins_2outs_ctrl(cond: %[[VAL_28]]: !esi.channel<i1>, data: %[[VAL_14]]: !esi.channel<i0>) -> (outTrue: !esi.channel<i0>, outFalse: !esi.channel<i0>)
|
||||
// CHECK: %[[VAL_35:.*]], %[[VAL_36:.*]] = hw.instance "handshake_cond_br3" @handshake_cond_br_in_ui1_ui64_out_ui64_ui64(cond: %[[VAL_27]]: !esi.channel<i1>, data: %[[VAL_25]]: !esi.channel<i64>) -> (outTrue: !esi.channel<i64>, outFalse: !esi.channel<i64>)
|
||||
// CHECK: %[[VAL_21]], %[[VAL_37:.*]] = hw.instance "handshake_fork5" @handshake_fork_in_ui64_out_ui64_ui64(in0: %[[VAL_32]]: !esi.channel<i64>, clock: %[[VAL_4]]: i1, reset: %[[VAL_5]]: i1) -> (out0: !esi.channel<i64>, out1: !esi.channel<i64>)
|
||||
// CHECK: %[[VAL_23]] = hw.instance "arith_addi0" @arith_addi_in_ui64_ui64_out_ui64(in0: %[[VAL_35]]: !esi.channel<i64>, in1: %[[VAL_37]]: !esi.channel<i64>) -> (out0: !esi.channel<i64>)
|
||||
// CHECK: hw.output %[[VAL_36]], %[[VAL_34]] : !esi.channel<i64>, !esi.channel<i0>
|
||||
// CHECK: }
|
||||
|
||||
handshake.func @main(%arg0: none, ...) -> (i64, none) attributes {argNames = ["inCtrl"], resNames = ["out0", "outCtrl"]} {
|
||||
%0:4 = fork [4] %arg0 : none
|
||||
%1 = constant %0#2 {value = 1 : i64} : i64
|
||||
%2 = constant %0#1 {value = 42 : i64} : i64
|
||||
%3 = constant %0#0 {value = 1 : i64} : i64
|
||||
%4 = buffer [1] %13#0 {initValues = [0], sequential = true} : i1
|
||||
%5:4 = fork [4] %4 : i1
|
||||
%6 = mux %5#3 [%0#3, %trueResult_2] : i1, none
|
||||
%7 = mux %5#2 [%2, %trueResult] : i1, i64
|
||||
%8:2 = fork [2] %7 : i64
|
||||
%9 = mux %5#1 [%3, %14#0] : i1, i64
|
||||
%10 = mux %5#0 [%1, %15] : i1, i64
|
||||
%11:2 = fork [2] %10 : i64
|
||||
%12 = arith.cmpi slt, %11#0, %8#0 : i64
|
||||
%13:5 = fork [5] %12 : i1
|
||||
%trueResult, %falseResult = cond_br %13#4, %8#1 : i64
|
||||
sink %falseResult : i64
|
||||
%trueResult_0, %falseResult_1 = cond_br %13#3, %9 : i64
|
||||
sink %falseResult_1 : i64
|
||||
%trueResult_2, %falseResult_3 = cond_br %13#2, %6 : none
|
||||
%trueResult_4, %falseResult_5 = cond_br %13#1, %11#1 : i64
|
||||
%14:2 = fork [2] %trueResult_0 : i64
|
||||
%15 = arith.addi %trueResult_4, %14#1 : i64
|
||||
return %falseResult_5, %falseResult_3 : i64, none
|
||||
}
|
||||
|
|
@ -21,6 +21,7 @@ target_link_libraries(circt-opt
|
|||
CIRCTFSM
|
||||
CIRCTHandshake
|
||||
CIRCTHandshakeToFIRRTL
|
||||
CIRCTHandshakeToHW
|
||||
CIRCTHandshakeTransforms
|
||||
CIRCTLLHD
|
||||
CIRCTLLHDToLLVM
|
||||
|
|
|
|||
Loading…
Reference in New Issue