* [Support] Factor appendPossiblyAbsolutePath() into lib/Support.
This was duplicated between ExportVerilog.cpp and BlackBoxReader.cpp,
but it is a generally useful utility function.
* [HWExportModuleHierarchy] Directly emit JSON to a file instead of an sv.verbatim op.
Previously this pass created an sv.verbatim op with the entirety of the
module hierarchy JSON file embedded into it, with the expectation that
the --split-verilog mode of firtool would actually be the one to create
it. This is now problematic because we'd like to move name legalization,
into the ExportVerilog pass, which means module names could change after
ExportVerilog runs.
Moving the HWExportModuleHierarchy pass after ExportVerilog guarantees
that names match the final verilog, but that means that
HWExportModuleHierarchy may no longer rely on the sv.verbatim op
output_file method to actually emit the file.
This commit changes HWExportModuleHierarchy to directly write the module
hierarchy JSON files. Note that firtool will now only run the
HWExportModuleHierarchy pass when --split-verilog mode is enabled, since
we now only want to run it when we have an output directory to dump
files to.
I misunderstood how this worked and accidentally broke it: it isn't printing
anything itself, it is mutating the IR and having verilog emission print its
output.
Move singleton headers like circt/Conversion/LLHDToLLVM/LLHDToLLVM.h
up to circt/Conversion/LLHDToLLVM.h since that is the only thing in that
directory.
This also moves HWLegalize*Names next to it, in preparation for it being
slurped in. This, in turn, allows us to run it before
HWExportModuleHierarchy pass.
ExportVerilog was initially conceived as a translation that read the
IR and printed out verilog text. However, it evolved to being a pass
that mutates the IR (e.g. its prepare pass). As such, it makes more
sense to model it in CIRCT as a transformation: we want to be able to
run passes after it in the pass pipeline, e.g. to generate metadata.
This takes one step towards that, adding new entrypoints that make it
available in circt-opt.
Add a new option to firtool, "--omir-file <file>", which will parse an
Object Model 2.0 JSON file into an OMIRAnnotation. This only handles
parsing. No scattering is performed.
Add one test that the "--omir-file <file>" option used to ingest an
Object Mdoel 2.0 JSON file works for firtool. Check that the
information in the OMIR is preserved and is wrapped in an
OMIRAnnotation on the circuit.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Add a first implementation of Grand Central's `EmitSignalMappings` pass,
which populates a module in a circuit with `force` statements and
cross-module references that access things in a second circuit. This
requires a lot of polishing and ironing out of kinks and the design in
general later, but this is a first bare-bones implementation in the
spirit of the other Grand Central passes (use verbatim SV to get
something going, even if it's brittle and needs some cleaning up later).
To avoid having to deal with the issue that `EmitSignalMappings`
actually operates on two circuits in parallel, the current
implementation only operates on the circuit where the `force` statements
are to be inserted, and uses some text manipulation to guess what name
the forced/probed things in the remote circuit will end up having in the
output Verilog. This will need proper XMRs in the future, but works as a
first shot.
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This commit refactors the handshake-runner to be based on a visitor pattern rather than manually checking for the type of each possible operation. The commit takes a step towards reducing the code duplication between executing a mlir::FuncOp and handshake::FuncOp. Many more opportunities for cleanup and refactoring exists, however, I decided to focus on wrapping the existing code into a visitor for this commit.
Since this is creating verbatim operations instead of emitting files
directly, `create` makes more sense as a verb.
Since the metadata emitted is specific to SiFive build flows, this
renames the pass to make it clear that it is not generically useful.
This leaves the pass on by default since the pass will only do anything
if the correct annotations exist.
This change was suggested here:
https://github.com/llvm/circt/pull/1875#discussion_r716070526
This adds another metadata emitter. This purpose of this pass is to
collect every blackbox module (or extmodule) which will need to be
stubbed or filled in. This excludes blackbox modules which have inlined
or imported verilog.
There are two separate metadata files generated for this: one for
blackboxes instantiated under the DUT as denoted by the
MarkDUTAnnotation. The other is a list of blackboxes not instantiated
under the DUT.
This is currently a simple class that traverses pairs of Affine memory
access operations and uses the upstream `checkMemrefAccessDependence`
function. The results are stored in a convenient data structure that
can be queried to inform scheduling decisions. A test pass is added,
which outputs the results as attributes for verification.
Add a pass to handle all annotation scattering. This pass is table driven, with customizable scattering per-annotation-class. When this is fleshed out, it will replace the annotation handling code in the parser.
Right now, this supports a couple testing annotation to make test cases against.
Until this is live in the pipelines, add an option to the parser to bypass annotation handling and scattering to enable testing.
* [LowerToHW] Lower mainModule and DesignUnderTest attributes into moduleHierarchyFile attribute.
Since these are currently only used for the export module hierarchy
pass, these have been replaced with a more generic attribute marking
which modules should have their hierarchies exported to output files.
* [SV] Add ExportModuleHierarchy pass.
This adds a pass that collects the full module hierarchy into a JSON
string, which is then exported as part of an sv.verbatim op. The pass
collects a hierarchy for each module with the firrtl.moduleHierarchyFile
attribute.
The pass can be enabled in firtool by providing the
--export-module-hierarchy option.
This adds the prefix-modules pass to FIRRTL. This pass looks for
modules annotated with the `NestedPrefixModulesAnnotation` and prefixes
the names of all modules instantiated underneath it. This pass will
duplicate modules as necessary to give submodules unique names. The
annotation can be attached to module definitions, as well as specific
instances.
The supported annotation is:
```json
{
class = "sifive.enterprise.firrtl.NestedPrefixModulesAnnotation",
prefix = "MyPrefix_",
inclusive = true
}
```
If `inclusive` is false, it will not attach the prefix to target module,
only to modules instantiated underneath it.
* [Handshake] Refactor handshake tablegen files
No functional changes; this commit creates an identical structure to the rest of the dialects in CIRCT wrt. how and where the various TableGen'erated files are included.
Just pass down the output filename instead of a lambda, there is no
need for the extra abstraction here. While here, change the timer
in the various flavors of output to be more specific than "Output".
* [Handshake] Support handshake.InstanceOp in handshake-runner
This commit adds support for executing handshake.InstanceOp operations in the handshake-runner.
This is enabled by mostly leveraging the existing executeHandshakeFunction function. When encountering an InstanceOp, a new value- and time map is created, representing the values accessible within the scope of the function referenced by the InstanceOp. In this map, associations between the operands passed to the InstanceOp and the SSA names of the arguments of the function that the InstanceOp references, are created. Return values from the InstanceOp are inserted into the valueMap of the enclosing (caller) scope.
Apart from this, made a slight modification to the structure of the handshake-runner; split up a few functions as well as added an enclosing class to reduce the number of arguments being passed around (i.e., the store, which is global across all std.op executions, InstanceOp executions, etc.).
BlackBoxMemory creates modules with bundles types to replace memory
operations. If this runs after LowerTypes, then we hit the LowerToHW
pass with a bunch of bundle types around. This pass is not often used,
and this must have regressed at some point.
This also adds an integration test to ensure that CHIRRTL memories are being
properly lowered to verilog.
This pass provides a structured way to handle IR features that are not
supported by all tools, and this lowering option reflects a specific
limitation of the Yosys tool.
Right now the pass isn't super helpful: it just rejects unsupported operations
with an error. This is progress towards Issue #1592.
This adds an implementation of the RemoveCHIRRTL pass called
LowerCHIRRTL. This pass takes the CHIRRTL memory operations, `seqmem`
and `combmem`, and transforms them into standard FIRRTL `mem`
operations.
Co-authored-by: Andrew Lenharth <andrew@lenharth.org>
Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>
Co-authored-by: Andrew Young <youngar17@gmail.com>
Add a `--parse-only` option to `firtool` which causes the program to
stop after the FIR/MLIR and annotation input files have been parsed and
processed, and writes the resulting MLIR module to the output. This is
interesting and useful since `firtool` performs a unique combination of
input translation and annotation scattering that is not trivially
reproduced with `circt-translate` and `circt-opt`. Useful for test case
reduction.
- Update/rewrite the `circt-reduce` tool with a custom proof-of-concept
reducer for the FIRRTL dialect. This is supposed to be a pathfinding
exercise and just uses FIRRTL as an example. The intent is for other
dialects to be able to produce sets of their own reducers that will
then be combined by the tool to operate on some input IR.
At this point, `circt-reduce` can be used to reduce FIRRTL test cases by
converting as many `firrtl.module` ops into `firrtl.extmodule` ops as
possible while still maintaining some interesting characteristic.
- Extend `circt-reduce` to support exploratively applying passes to the
input in an effort to reduce its size. Also add the ability to specify
an entire list of potential reduction strategies/patterns which are
tried in order. This allows for reductions with big effect, like
removing entire modules, to be tried first, before taking a closer
look at individual instructions.
- Add reduction strategies to `circt-reduce` that try to replace the
right hand side of FIRRTL connects with `invalidvalue`, and generally
try to remove operations if they have no results or no users of their
results.
- Add a reduction pattern to `circt-reduce` that replaces instances of
`firrtl.extmodule` with a `firrtl.wire` for each port. This can
significantly reduce the complexity of test cases by pruning the
module hierarchy of unused modules.
- Move the `Reduction` class and sample implementations into a separate
header and implementation file. These currently live in
`tools/circt-reduce`, but should later move into a dedicated reduction
framework, maybe in `include/circt/Reduce`, where dialects can easily
access them and provide their own reduction implementations.
* Extract reset-related test cases from the existing Scala FIRRTL
compiler code; specifically from `InferResets`, `CheckResets`,
`RemoveReset`, and `FullAsyncResetTransform`.
* Add the `InferResets` transformation pass to the FIRRTL dialect, which
assigns asynchronous resets to registers without reset, and replaces
`reset` types with either `uint<1>` or `asyncreset`, as appropriate.
* Add the `--infer-resets` option to firtool, on by default.
Inlining and IMConstProp generate additional opportunities for
canonicalization, especially around registers with invalid/constant
reset signals and values. To leverage these, firtool should run the
canonicalizer again just before going into the output-specific
pipelines.
Add the `--split-input-file` and `--verify-diagnostics` options to
firtool. This brings it more in line with other tools such as circt-opt,
and simplifies writing integration tests against firtool.
Add a `circt-reduce` utility, which basically follows the "build a
custom mlir-reduce" steps described in the MLIR documentation. The
intent here is to have a first step towards a CIRCT-specific reduction
utility. At a later stage, we may want to start populating the reducer
framework with reduction patterns specific to CIRCT (like fan-in/-out
cone isolation, port removal, etc).
This pass runs a strongly connected components (SCC) detection to check
combinational cycles in the IR. The current implementation assumes the
firrtl-lower-types and firrtl-expand-whens has been applied before this pass.
This turns on the FIRRTL inliner by default. This pass has some
questionable behaviour where it will delete any module not reachable
from the top level module. This is an optimization that prevents the
pass from performing uneccesary work, while not leaving unprocessed
modules in the code. This is also the mechanism through which modules
which had all instances inlined will be deleted. We may want to decide
if this behaviour is desirable before merging this commit.
Merge the `CheckWidhts` pass into the `InferWidths` pass, which already
has all the necessary information to complain to the user about
uninferred widths. This commit also improves error reporting a bit by
tracking additional location information on the constraint expression
such that we can point the user at the sites where a connection may
cause problems.
Fixes#1297.
In a couple of places in our build system, we wanted to create targets
that depended on generated files. We were not passing the full path to
the generated files, e.g. `CosimScheme.h`, and CMake was unable to find
the it. CMake was then searching the current directory for a
matching file with a prefix, and would find the unprocessed
file, e.g. `CosimSchema.h.in`, and use that instead. A policy change
CMP0115 in newer version of CMake causes this to spit out many warnings
about it how it will no longer search for source files. For more
information about the policy see
https://cmake.org/cmake/help/latest/policy/CMP0115.html
This change provides the full path to the generated file, which allows
cmake to find the intended file and not produce so many warnings.
Rewrite LowerTypes to simplify and improve performance.
Walks the operations in reverse order. This lets it visit users before defs. Users can usually be expanded out to multiple operations (think mux of a bundle to muxes of each field) with a temporary subWhatever op inserted. When processing an aggregate producer, we blow out the op as appropriate, then walk the users, often those are subWhatever ops which can be bypassed and deleted. Function arguments are logically last on the operation visit order.
Each processing of an op peels one layer of aggregate type off. Because new ops are inserted immediately above the current up, the walk will visit them next, effectively recusing on the aggregate types, without recusing. These potentially temporary ops (if the aggregate is complex) effectively serve as the worklist. Often aggregates are shallow, so the new ops are the final ones.
There is no global map. When you update an aggregate producer, you build a small vector of it's expansion, which you use to update it's users. Once the users of an aggregate are updated, there is no reason to store mapping data on them any longer.
This structure makes it relatively easy to to do connect-expansion and partial-connect-legalization along the way. connects get processed before their source and dest.
This gives a 40% improvement on a medium sifive core and hasn't been tuned yet.
Co-authored-by: Prithayan Barua <prithayan@gatech.edu>
Co-authored-by: Prithayan Barua <prithayan@gmail.com>
Emit a warning after lowering `FIRRTL` operations to `HW` dialect,
if there are `annotations` remaining on the `FIRRTL` operation.
This is required to detect missing passes in FIRRTL dialect to remove the annotations.
The warnings are disabled by default.
- Use a set to record all the annotations remaining on different operations.
- Emit a warning for each annotation only once. So if the same annotation is found on different operations, only one warning is emitted.
- Add an option to `LowerFIRRTLToHW` pass to enable the warnings
- The option is disabled by defailt
- Use`emit-annotation-warning=true` to emit the warnings
- Add option `emit-annotation-warning` to `firtool` , which should be passed to `createLowerFIRRTLToHWPass`
- Note: The `emitWarn` will crash when trying to print the `InstanceOp`. Reason for crash:
1. If we try to print the old `InstanceOp` operation while traversing the operations in a module, the symbol referring to the module is invalid. Hence `getReferencedModule` crashes.
2. The traversal is on the new temporary module body, which has moved(`splice`) the old operations, https://github.com/llvm/circt/blob/main/lib/Conversion/FIRRTLToHW/LowerToHW.cpp#L825
3. Seems like the original symbol on the operation gets deleted during the `splice`, hence the invalid temporary IR.
- To fix the crash, we don't print the operations by using `mlir::emitWarn`, and just print the source location.
- Use `std::mutex` when updating the `StringSet<> alreadyPrinted` in class `CircuitLoweringState`
- `CircuitLoweringState` object is shared between threads working on modules, hence the lock is required when updating the set. (https://github.com/llvm/circt/blob/main/lib/Conversion/FIRRTLToHW/LowerToHW.cpp#L208)
* Add a `GrandCentralTaps` pass which consumes the FIRRTL Grand Central
data and memory taps annotations, and generates the corresponding
blackbox data tap modules with hierarchical Verilog identifiers
inside.
* [FIRRTL] Add Grand Central Interface Support
* [FIRRTL] Add Grand Central Interface Tests
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
We previously disabled multithreading when parsing the input file
to save cost on some mutexes etc, since the parser wasn't threaded.
Now however, the verifier is threaded, and disabling multithreading
is disabling it as well.
Just stop doing this. This provides an aggregate speedup for me,
e.g. shrinking total firtool time from 29.9s to 26.7s on a large
design (18.6s -> 15.2s in the parser) which is a pretty big speedup.
It was decided that "black box" should be consistently used as two words
in the code base. See #1209.
```
Blackbox -> BlackBox
the blackbox -> the black box
```
To paraphrase Aliaksei over slack, "The people always wanted
imconstprop, what could possibly go wrong" 🙈
Admittedly, I might be paraphrasing that wrong.
This pass has been subjected to fuzz-testing for quite some time, and it
is surprising (in a negative usability sense) that it is not enabled by
default.
Some FIRRTL-to-LLHD tests were using firtool with uninitialized ports,
and this change switched them to use circt-translate instead.
* In addition to the `--blackbox-path` option which specifies the
overall search path for black box files (including `BlackBoxPathAnno`
annotations), add a separate `--blackbox-resource-path` option which
only affects the `BlackBoxResourceAnno` annotations. These get moved
into the Scala/sbt artifacts directory, and the resource path should
generally point there. Path annotations in general will want to remain
relative to the input FIR file, which this additional enables.
* Move the width inference pass up in the pipeline such that it runs
before the canonicalization passes. This is useful since width
inference itself does not depend on canonicalization, but in turn
enables a lot of canonicalization patterns to run.
* Add the `BlackBoxReader` transformation pass which is modeled after
the `BlackBoxSourceHelper` Scala implementation. It honors a set of
FIRRTL annotations that declare source code for black boxes to be
copied to an output directory. This pass reads those source files into
an operation in the IR, such that they can be written to the output
during emission. Annotation can be done inline, as a separate path, or
the rather Java-specific resource mechanism.
Required changes:
- The vector namespace in MLIR was colliding with the std::vector type
- Missing MemRef dialect dependency in circt-opt
- Missing Standard dialect dependency in ExportLLHD
This makes sure not to rename FIRRTL to HWRTL :-), and I spot checked a
many things to avoid changing general references to RTL (e.g. when referring
to external tools) but I suspect that I missed some. Please let me know (or
directly correct) any mistakes in this mechanical patch.
The difference is that we no longer run the dtor for the MLIRContext
that we parse a bunch of IR into. This avoids spending time
deallocating memory, which is pointless immediately before process
exit.
* Use the new `TimingManager` in MLIR to include the parser and output
emitter in the timing statistics.
* Renames the `--pass-timing` option to `--mlir-timing`.
Fixes#608.
This incurs some cost in the generated simulator. Monitoring and saving the
waveforms to disk incurs yet more overhead, so enable this via an environment
variable.
* Run the `CheckWidths` pass when lowering to the RTL dialect to ensure
there are no uninferred widths that will cause the lowering to fail.
* Add a `--infer-widths` option that runs the `InferWidths` pass.
Fixes#1032.
The module inlining pass handles module flattening and instance
inlining. Module flattening is recursively inlining every instance in a
module. Module inlining is inlining only the instances of modules
which are marked for inlining.
This includes a couple breaking changes:
* AttrDef has a new argument for attribure traits.
* Several includes we depended on appear to have been moved to forward
declarations, so add the explicit includes we needed.
* Stop generating stub files for external modules when split Verilog
output is enabled. This will collide later with black box annotations
supplying the actual files to be included for external modules.
* Rather than printing the list of emitted files to standard output,
generate a dedicated `filelist.f` file for split Verilog output with
one line for each emitted file.
Canonicalize does a bunch of stuff that is slow and not useful for either
the RTL or the firrtl dialects, because it is heavily focused on CFG-like
things. We'll trim some of this fat out in our local clone, as the main
MLIR canonicalizer is carrying some significant compatibility issues that
make it difficult to improve.
This ports the expand whens pass from the Scala FIRRTL compiler. This
pass handles last connect semantics, and replaces all When operations
with equivalent statements. For example:
```firrtl
module MyModule :
input en: UInt<1>
input a: UInt
input b: UInt
wire w: UInt
when en :
w <= a
else :
w <= b
```
is expanded to:
```firrtl
module MyModule :
input en: UInt<1>
input a: UInt
input b: UInt
wire w: UInt
w <= mux(en, a, b)
```
Model of the compreg op outlined in the Seq dialect rationale dialect. This is just a starting place and I do expect it to change and/or have siblings for different flavors. Lowers to sv.alwaysff with posedge clock and sync reset -- for now.
Also adds a few mechanical things required to make the Seq dialect actually work which I neglected in the PR which added the dialect.
This change adds the ability to control the verilog emitter using a set
of attributes on the top level ModuleOp. This is controlled by an
attribute key on the top level module, `circt.loweringOptions`, with a
StringAttr parameter.
This adds a command line option which will amened the IR after parsing
with the options.
The options used in the attribute and the commandline match.
Small logical bug enabled mulithreading while passes were being executed
unconditionally. This change saves the multithreaded mode and restores
it to the previous value.
The compiler can parallelize pass which are running on distinct
IsolatedFromAbove operations. Moving these passes to run on the
FModuleOp will increase the ability of the compiler to parallelize their
execution. Since there are no operations under the CircuitOp other than
FExtModule and FModule, this does should not change what gets CSE'd and
Canonicalized.
* Refactor the MLIR module level emission in ExportVerilog such that it
has a separate but symmetrical `UnifiedEmitter` and `SplitEmitter`.
These either emit Verilog into one large file, or one separate file
per module and interface. This will also provide a way to inject the
results of LegalNamesAnalysis into the emission process.
* Add `isNameValid` to SV dialect to check if a string contains only
characters that are legal for SV identifiers.
* Verify that module names contain only allowed characters when emitting
them in ExportVerilog. Do no longer sanitize the module names but rely
on a separate pass on the IR to do so.
* Run the RTLLegalizeNamesPass when emitting Verilog with firtool.
* Check for name consistency in split-verilog test case.
* Run `circt-opt --rtl-legalize-names` before `circt-translate
--export-verilog` to ensure names are legal for emission.
* Update the expected output in the rtl-dialect.mlir test, since the
separate renaming pass now ensures that the two `arrZero` ports do no
longer conflict in the output. Also the index on `reg_2` has shifted
by one due to an intentional conflict caused through `inout_0` to
check for proper renaming.
* Add explicit check for sanitization of an instance with unsavoury
name.
* Rename the `rtl.module.extern @reg` in the sv-interfaces.mlir test,
since the renaming pass cannot just go rename external modules. This
should probably become an error check at a later stage.
* Emit a diagnostic in the `RTLLegalizeNamesPass` if an extern module
has an invalid name.
* Add test cases that check for these diagnostics.
* [FIRRTL] Parse local Circuit, Module Annotations
Adds the ability to parse and store CircuitTarget or ModuleTarget local
Annotations as MLIR Attributes. Annotations are stringly-typed and stored
in an ArrayAttr. The "target" field is removed as part of this process as
this is now implicit based on the operation to which the Attribute is
applied.
Other types of Annotations (e.g., ComponentTarget or non-local) produce a
runtime error.
The utility firtool is updated to take an --annotation-file argument which
can be used to import annotations from an annotation file. Additionally,
annotations can be specified using a new "inline" syntax on a FIRRTL
circuit using `%[annotations]`. Any --annotation-file annotations are
appeneded to inline annotations if they exist.
Add tests of CircuitTarget, ModuleTarget, CircuitName, ModuleName, and
erroneous/unsupported annotations or JSON.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Make the `reservedWordCache` thread-safe by using a constructor class
for the underlying `llvm::ManagedStatic`. Also simplify the whole
thing by dropping the `getReservedWords()` function and renaming the
static to `reservedWords`.
* Parallelize split Verilog emission
* Print file list for split Verilog output
This is needed to fix a crash in DCE for graph regions. [0]
- alloc and store operations have been moved to a new MemRef dialect
- custom dialect types now need to be registered in the same compilation
unit as the type's storage. Any dialect that registers types have had
the logic moved to DialectTypes.cpp.
- Small change to the ResetTypeAttr default value declaration.
[0] https://reviews.llvm.org/D98919
This adds a -shared-libs option to llhd-sim that is analogous to the
same option for mlir-cpu-runner. If specified, those libraries are
passed to the ExecutionEngine to dynamically load and link.
* Separate the `processBuffer` function into two parts: one that
processes the input buffer into a module, and one to emit that module
to an output stream.
* Make processBuffer take callback to process module
* Add another output format which emits a separate verilog file for each
module in the IR.
* Add a `SplitModuleEmitter` to `ExportVerilog` which creates files as
it walks over the module body and uses the existing `ModuleEmitter` to
spit out operations.
* `sv.verbatim` and `sv.ifdef.procedural` are currently treated as
having file-scope (rather than compilation-unit-scope) and are emitted
into every file. Since this is currently mostly preprocessor business,
it does this by gobbling up operations, and thus only perviously seen
ops are actually emitted. This can go horribly wrong.
* Add test
Now that the module bodies are processed in parallel, we can eliminate this
split. This will open the door to significantly simplify the implementation,
but tries to take on the bulk of the testcase updates without permuting the
pass implementation too much.
Some changes in this bump:
* OpBuilderDag -> OpBuilder: github.com/llvm/llvm-project/commit/32c49c7
* Changes to Type getChecked and verification: github.com/llvm/llvm-project/commit/06e25d5
* Changes to Value internals, with minor public breakage: github.com/llvm/llvm-project/commit/3dfa861
* Changes to LLVM translation: github.com/llvm/llvm-project/commit/19db802
* .getAttrs() -> ->getAttrs():
* Adding llvm_unreachable after covered switch statements with returns
* Separating diagnostics tests from FileCheck tests
[FIRRTL LowerTypes] Add FExtModule type lowering
This adds FExtModule lowering support to the lower types pass. This
flattens all types in the parameter list and gives each new operand a
new name.
To process ExtModules in this pass, it had to change from a FModuleOp
pass to a CircuitOp pass. In order to maintain performance, this pass is
now parallelized internally using `parallelFor`.
This is the start of some work to add a pass to automatically create
black boxes for FIRRTL memory operations. This works by replacing a
firrtl.mem op with an equivalent instance of an external module. This
work aims to add a feature to replace the --repl-seq-mem option in the
SFC.
This new blackboxing pass is storing the memory configuration data as
parameters on the generated external module. The hope is that we
can write a pass or tool which can launch a (command line) registered
generator to produce whatever artifacts we need. A larger discussion
about how this should work will probably be necessary.
Module name collisions are avoided by manually inserting new modules in
to the symbol table. This uses the built in symbol collision handling
in MLIR.
The generated modules are deduplicated by specialized hash and equality
functions which compare the memory attributes and return types, ignoring
the naming. This lets us deduplicate black box modules which (I think)
cannot be deduplicated by other passes.
This pass can optionally inline the generated wrapper module directly,
skipping the need to generate it.
It can be really helpful to disable the verifier in order to dump all of
the IR at a later point. This option is already supported by circt-opt,
but it can be useful here as well.
This change aims to remove all instances of `using namespace mlir` from
our header files. Many types have been manually imported into the
`circt` namespace in `circt/Support/LLVM.h`. These types include all
core MLIR functionality types (IR, Diagnostic), utility types, rewrite
patterns and conversions, builtin IR types and attrs, and the module op.
Not imported were any operations (other than ModuleOp), matchers (e.g.
m_Zero), anything in the `impl` namespace, and interfaces. There are
some problems with interface code generation from ODS, so some
interfaces were imported.
Some further cleanup would be useful to remove the `mlir::` namespace
qualifier where we no longer need it.
This combines all conversion passes into a single Passes.td similar to
MLIR. For some conversions, the passes were not specified using ODS.
These passes have been converted to use ODS which means they will show
up in generated documentation. Conversion passes have also been moved
out of dialect namespaces, it is normal for them to live under the CIRCT
namespace.
This adds a pass to merge `sv.alwaysff` operations with identical
conditions. Due to the design of this operation it is trivial to check
if we meet the conditions for merging this operation. This pass is
structured to not depend on the RTL dialect, and does not assume that
the `sv.alwaysff` operations are in an RTL module. They do, however,
need to be in a graph region to work.
Although `sv.alwaysff` regions are not graph regions, they are limited
to having a single block. This pass takes advantage of this to quickly
splice blocks together when merging operations.
This change cargo-cult imports InitAllDialects.h and InitAllPasses.h
from MLIR.
`circt-opt` has been greatly simplified by using the more powerful
version of `MlirOptMain`, which supersedes all our current
command line options.
Now we're not preloading all dialects, we need to make sure that target
dialects are properly registered in all conversion passes. Source
dialects do not need to be manually loaded.
One thing which is not clear is if `circt::registerAllDialects` should
register any standard MLIR dialects which are used heavily throughout
CIRCT. This change only registers CIRCT dialects.
Selecting the port to use in `esi-cosim-runner.py` and then starting the
simulation to open it created a race condition. There's a brief period
of time between port select and simulator DPI execution in which another
process could open that port. Turns out this happens more often than I
originally anticipated.
Adds a test of the full ESI system:
- Lowers ESI channel ports to SV interfaces for externmodules.
- Adds pipeline stages via ESI buffer ops.
- Uses cosim to get data in/out.
Adds a simple loopback test and changes/fixes to enable it.
- Uses all the lowering passes to get everything in the RTL dialect.
- Uses circt-translate --emit-verilog to emit verilog.
- Uses circt-translate -emit-esi-capnp to get RPC schema.
- Runs it via esi-cosim-runner.py.
Richard Xia