Commit Graph

8413 Commits

Author SHA1 Message Date
Andrew Young b98d7f65e5 [FIRRTL][CheckCombLoops] rename test to match pass name, nfc 2024-06-18 08:45:43 -07:00
Andrew Young 6201aae645 [firtool] Move SpecializeLayers before LowerLayers
We can't specialize away layers after they are lowered, so this pass was
placed in the wrong spot in the pipeline. It was a last minute change to
move specialize layers after checking for combinational loops which
caused this bug, as we need to make sure that all diagnostic passes run
before we start deleting logic, otherwise we can hide errors from the
user.  This adds a few tests that layer specialization is working as
intended, and that it doesn't prevent detection of errors.
2024-06-18 08:45:22 -07:00
Andrew Young 28986b8b98 [firtool] verify that comb loop checking resolves last connects 2024-06-18 08:45:22 -07:00
Andrew Young baec1a1db1
[FIRRTL][SpecializeLayers] Fix incorrect CF leading to double free (#7200)
As a part of specializing layers we have to remove any HierPathOps which
included a reference to deleted instances.  If any member of the path
array is contained in the deleted references list, we need to delete the
op.  There was incorrect use of `continue` which caused us to continue
processing the path instead of skipping to the next path operation,
which could lead to a double free when multiple instances in the path
were removed.
2024-06-18 08:42:26 -07:00
fzi-hielscher d340ca137c
[NFCI][OM][SSP][SystemC] Refactor TableGen Pass includes (#7184) 2024-06-18 14:52:24 +02:00
fzi-hielscher 15ae39ec07
[NFCI][DC][FSM][Handshake][Pipeline] Refactor TableGen Pass includes (#7181) 2024-06-18 13:26:12 +02:00
Andrew Young a49e31d60e
[FIRRTL][SpecializeLayers] Update doc with proper attribute name (#7199) 2024-06-17 19:34:50 -07:00
Andrew Lenharth 6b6855910a [NFC] Add more clang options. From my reading of the docker file, most of them don't actually work since most clang versions are not installed. But regardless, do this in anticipation of different clang versions 2024-06-17 14:35:48 -05:00
Andrew Lenharth 89bc24690d [NFC][FIRRTL] Narrow type for SizedType. 2024-06-17 11:28:48 -05:00
Andrew Lenharth 0046bab73a [NFC][FIRRTL] Narrow SizedPassiveType to FIRRTLBaseType 2024-06-17 11:23:59 -05:00
Hideto Ueno 97da411151
[ExportVerilog] Fix two state type emission of aggregate types (#7189)
This PR fixes an issue that `emitAsTwoStateType` flag was not propagated for aggregate types.

This PR also fixes a bug that ctypes (int/shortint etc) are used as an inner type of packed types (e.g. `int [2:0]` is invalid) according to SV spec 6.8.
2024-06-18 01:14:50 +09:00
Hideto Ueno d1545f4f5a [LowerDPI] Fix the incorrect input type checking
LowerDPI checks that improted DPI functions have the same function
signatures over their call sites. This fixes a bug that mistakenly
regards operand types of call op as input types. Call op has clock and
enable operands so operand types are not equal to input types of
DPI functions.
2024-06-17 08:44:51 -07:00
fzi-hielscher 9afdd4d069
[NFCI][FIRRTL] Refactor TableGen Pass includes (#7178) 2024-06-17 16:18:07 +02:00
Hideto Ueno 3e67926aa3
[SimToSV] Fix DPICall lowering to use `replaceOp` (#7192)
Previously DPICallLowering called `rewriter.replaceAllUsesWith` for individual
results but it seems that is not equivalent to `replaceOp`. 

This also adds missing dialect dependency to seq

Close #7191
2024-06-17 19:44:20 +09:00
Hideto Ueno 18d2872d70
[FIRRTL][ExpandWhens] Add StmtExprVisitor to Visitor and Support DPI intrinsic in ExpandWhens (#7177)
This adds `StmtExprVisitor` struct for visitor to handle operations with an optional result. Currently `GenericIntrinsicOp `and `DPICallIntrinsicOp` are added.

Besides that `ExpandWhens` is modified to handle DPI intrinsic.
2024-06-17 06:21:11 +09:00
fzi-hielscher 28c29619c8
[NFCI][LLHD][Moore][SV][Verif] Refactor TableGen Pass includes (#7183) 2024-06-16 18:36:00 +02:00
fzi-hielscher f5378eb8d9
[NFCI][ESI][Ibis][MSFT] Refactor TableGen Pass includes (#7179) 2024-06-16 18:33:18 +02:00
fzi-hielscher f3054773df
[NFCI][Comb][HW][Seq] Refactor TableGen Pass includes 2024-06-16 18:29:59 +02:00
Robert Young b271e8ac9f
Add missing header includes (#7187) 2024-06-16 10:19:17 -04:00
Robert Young ae1b8f778e
Fix paths in tests for windows builds (#7185)
* Fix paths in tests for windows builds

* Fix patterns that check mlir: backslashes are rendered as double backslashes

* Fix fir emitter for output dirs with backslashes

* Try fixing patterns, again

* FIRLexer: parse escaped backslashes in strings

* Fix more patterns with backslashes

* This time, for an absolute path
2024-06-15 16:20:03 -04:00
Andrew Young c93ca4ecf4 [firtool] Support layer specialization 2024-06-14 15:48:53 -07:00
Andrew Young fbbf36f35a [FIRRTL] Add pass to specialize layers 2024-06-14 15:48:53 -07:00
Andrew Young 870a43ae38 [FIRRTL] InstanceChoiceOp: add method to erase ports 2024-06-14 15:48:53 -07:00
Andrew Young 0ffb67973f [FIRRTL] Passes.td: reflow whitespace, nfc 2024-06-14 15:48:53 -07:00
Amelia Dobis 0a81a3eb69
[Verif] Add PrepareForFormal pass (#7175)
This PR introduces a PrepareForFormal pass that tries to alleviate some of the heavy lifting being done in the btor emission. For now this only flattens wires, but in the future in will also handle formal contracts and anything else that is done to make emission for formal tools easier, which is why it's part of the verif dialect and not hw.

This is derived from #7150
2024-06-14 12:07:06 -07:00
Robert Young 41ebd04f88
[FIRRTL] Output directory control for layers and modules (#6971)
* Add getDirectoryAttr helper to HWOutputFileAttr

This helper gets the directory component of an output file name, or returns
nullptr if there is none.

* Output directory control v2

Instead of using an explicit precedence declaration anno to help guide the
assignment of floating modules to output directories, use the directory
hierarchy itself.  So if a module is used under directory A/B and A/C, it will
be placed into directory A.

* Support absolute output directories for modules

* Add comment

* Make it so output dir annos only apply to public modules

* Simplify lower layers

* Add ability to configure the output directory of assign-output-dirs

* Update tests

* Address review comments

* Clean up whitespace in test

* clang-format

* Fix up firtool integration test excercising dedup + output dirs

* Address review comments
2024-06-14 14:51:28 -04:00
fzi-hielscher 7690177154
[NFCI][Transforms] Refactor TableGen Pass includes (#7173) 2024-06-14 19:13:15 +02:00
fzi-hielscher 2554a14234
[NFCI][Calyx] Refactor TableGen Pass includes (#7182) 2024-06-14 18:55:51 +02:00
fzi-hielscher 0e22c2b27a
[NFCI][Conversion] Refactor TableGen Pass includes (#7174)
Refactor includes of TableGen passes in the "Conversion" sub-tree to the new style.
See #3962 , https://reviews.llvm.org/D143773
2024-06-14 16:37:29 +02:00
Hideto Ueno ff4c6218f3
[LowerDPI] Create a helper struct, NFC (#7176)
This is a preparation for another PR. Create `LowerDPI` struct and refactor the logic into several helper functions.
2024-06-14 23:10:08 +09:00
Hideto Ueno f32a5a196c
Bump llvm (#7167)
Bump to 00bb18a77c

* applySignatureConversion change 52050f3ff3
2024-06-14 14:38:46 +09:00
mingzheTerapines b136101756
[ImportVerilog][MooreToCore]Lower moore.namedConstant to hw.param.value (#7122)
* [mooretocore] Support namedconstant

Signed-off-by: mingzheTerapines <mingzhe.zhang@terapines.com>

* Limit type to integertype.

* add mooretocore support

* remove include

* remove verify of hwops

* remove include

* Test added.

* Add test for MooreToCore

* Support any attribute

* Modify test.

* Add symbol for wireOp

* Remove useless include

* Add more test and error cases

* slang-tidy

* some Imporvement

* Improved version

* little change

* Imporve

---------

Signed-off-by: mingzheTerapines <mingzhe.zhang@terapines.com>
2024-06-14 09:22:46 +08:00
Hailong Sun f26f534d60
[Moore] Add evenOp to handle event controls. (#7154) 2024-06-14 09:05:33 +08:00
fzi-hielscher 11fb804813
[NFC][ExportVerilog] Rename generated `options` member. (#7172)
Side-step an issue that prevents transitioning the inclusion of TableGen defined passes to the new(er) style.
2024-06-13 18:20:34 +02:00
Prithayan Barua fe133f85c9
[FIRRTL] Add a new op interface for combinational loop detection. (#7120)
Add a new CombDataflow op interface to FIRRTL.
This interface is used for specifying the combinational dataflow that exists in
 the results and operands of an operation. Any operation that doesn't implement
 this interface is assumed to have a combinational dependence from each operand
 to each result.
Currently only FIRRTL register and memory ops implement this interface, but it
 can be used in other dialects that intend to use the CheckCombCycles pass.
2024-06-13 08:54:24 -07:00
fzi-hielscher e6dec6778a
[LowerDPI] Defer deletion of call ops to prevent invalid access. (#7170) 2024-06-13 16:28:07 +02:00
Hideto Ueno 523e9b4163
[FIRTRL][ExportVerilog] Emit small integers on DPI function as two state C-compatible types (#7163)
This PR modifies ExportVerilog to emit two state types (`bit` in general) for DPI import op. Furthermore, for specific bit width (8, 16, 32 and 64) it emits C-types (byte, shortint, int and longint). 

This PR also rejects small integer types other than 8, 16, 32 and 64 bit width since  otherwise we have to use`bit` but they are passed by references in DPI. So this PR defines the ABI as "small integers are passed by values, and larger integers are passed by references.
2024-06-13 23:08:30 +09:00
Hideto Ueno 44becae000
[FIRRTL] Add DPI call intrinsic and lowering pass (#7139)
This PR adds DPICallIntrinsicOp and its lowering pass. DPICallIntrinsicOp is lowered into sim.func.dpi.call and sim.func.dpi ops. At FIRRTL level DPICallIntrinsicOp doesn't have symbols and instead LowerDPI pass accumulates call sites and creates symbols for dpi functions. LowerDPI pass directly lowers FIRRTL intrinsic into Sim dialect since FIRRTL doesn't have DPI/Function construct. LowerDPI pass could be simplified (or migrated into LowerToHW) once FIRRTL gets 1st class support for Function. Unrealized conversion cast is used to mix FIRRTL and HW type values before LowerToHW.
2024-06-13 20:54:00 +09:00
Hideto Ueno 2876be2297
[ExportVerilog] Avoid using interface pass for PrepareForEmission, NFCI (#7168)
ODS InterfacePass generates `canScheduleOn` method with a specified interface in a header file and currently we import every pass declaration through PassesDetail.h. Gcc/clang seem to compile when there is an unknown interface class but MSVC emits an error. So this PR avoids `InterfacePass` in ODS and manually implements `canScheduleOn` in PrepareForEmission.
2024-06-13 19:52:04 +09:00
Hideto Ueno ee7d59be99
[Sim] Add DPI func/call and lowering (#7042)
This PR adds DPI func/call op and SimToSV lowering. 

`sim.dpi.func` is a just bridge to `sv.func`. This op can be lowered into `func.func` in the future for Arc integration. 

`sim.func.dpi.call` represents SystemVerilog DPI function call. There are two optional operands `clock` and `enable`.

If `clock` is not provided, the callee is invoked when input values are changed. If provided, the dpi function is called at clock's posedge. The result values behave like registers and the DPI function is used as a state transfer function of them. `enable` operand is used to conditionally call the DPI since DPI call could be quite more expensive than native constructs. When `enable` is low, results of unclocked calls are undefined and in SV results they are lowered into `X`. Users are expected to gate result values by another `enable` to model a default value of results. For clocked calls, a low enable means that its register state transfer function is not called. Hence their values will not be modify in that clock.

A function that returns an explicit return is not supported yet.
2024-06-13 19:11:56 +09:00
Hailong Sun 2b16c06874
[Moore] Add the SimplifyProcedures pass. (#7161) 2024-06-13 11:05:17 +08:00
Hailong Sun 190c5f8bf7
[Moore] A new pass to delete local temporary variables. (#7082)
[Moore] Introduce Mem2Reg to elminate local variables.

Co-authored-by: Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
2024-06-13 10:25:57 +08:00
John Demme a4845f1f82 [ESI] Ripping out some dead capnp code
This code was being used to generate a C++ API, which we no longer do.
2024-06-12 23:47:53 +00:00
Amelia Dobis cef54eef1d
[firtool] Remove LTLToCore pass from verification-flavor=immediate pipeline 2024-06-11 12:04:23 -07:00
Prithayan Barua 02bec89ded
[FIRRTL][CreateSiFiveMetadata] Add the path to the DUT, in the SiFive metadata class (#7156)
This commit adds the DUT module instance path to the to the `SiFive_Metadata`
 class. This is required to generate the DUT instance path directly from the
 OMIR. This will be required to generate DUT relative hierarchy paths for
 memories in the seq_mems.json metadata, Since all paths are by default
 generated relative to the top level.
This commit creates a list of paths, to handle multiple DUTs even though the
 current designs will have a unique DUT.
2024-06-11 10:33:29 -07:00
Schuyler Eldridge d9a3a95cca
[FIRRTL] Bump minimum to 2.0.0, remove partial conect (#5075)
Bump minimum supported FIRRTL to 2.0.0.
"FIRRTL version" is now required as a result.

Remove parsing of the FIRRTL partial connect operator ("<-").  This has,
for a very long time, been almost unreachable from Chisel-emitted FIRRTL
and is now impossible to emit from Chisel.  This has also been completely
removed from the FIRRTL spec in version 2.0.0.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Will Dietz <will.dietz@sifive.com>
2024-06-11 11:07:18 -05:00
Will Dietz 640d59cf0d [FIRRTL] Fix test (strictconnect -> matchingconnect). 2024-06-11 08:39:02 -05:00
Will Dietz abf780de76
[FIRRTL][Parser] Never use forceable (#7137) 2024-06-11 08:35:36 -05:00
Will Dietz 13a22290c4
[FIRRTL] Emulate tap-as-passive for no-ref-ports option. (#7109)
Taps (using probes) support a non-passive source with a passive sink (by their nature), but the hidden option to avoid probes does not.

Detect this specifically and fix by using passive type for wiring from source.

This allows taps of non-ground (non-passive) that work with probes to also work with this option.
2024-06-11 08:34:12 -05:00
John Demme 38bb2b4e7a [PyCDE] Fix importing extern modules
- Get module argument types from input_types rather than block arguments.
- Recognize HWModuleExtern as a module
2024-06-11 04:57:13 +00:00