* [ImportVerilog]Support union types.
* [ImportVerilog]Rename structMember with structLikeMember
* [ImportVerilog] check the type of new Expressions.
* [ImportVerilog]Add value check for new Expressions.
* clang-format modify recommand
* [importVerilog]Remove useless inlcludes
* [ImportVerilog]Add union size and domain
* [ImportVerilog]Give more specefic errors
This has only been used for probes, but without input probes
this is no longer useful or necessary.
The HW-signal hoisting works well (if limited) and has no
known issues[1] but has yet to be used in practice due
primarily to passthroughs being intentional occasionally
and lacking a mechanism to capture or distill this intent
properly (it must be ""optimized"" yet not).
Since this is unused, and lacking traction on the above,
remove from pipeline and delete this for now instead of
having it bitrot and be a maintenance burden while
adding/completing new features.
Lives on in version control history!
[1] FWIW, see https://github.com/llvm/circt/pull/6115 for
both small example and before/after on chipyard, as well
as testing internally back when this was introduced.
Add the `FindInitialVectors` pass to the Arc dialect which finds
isomorphic operations at the same topological rank and groups them into
`arc.vectorize` ops. This is going to be the starting point for later
canonicalizations and optimization steps to improve the vectors and
apply a cost model.
Move the definitions of packed and unpacked struct types from C++ land
into `MooreTypes.td`. This removes a significant amount of complexity.
With all types moved into the TableGen file, a lot of redundant code can
finally be removed and the parsing/printing can be streamlined
significantly.
This change also drops the `StructKind` enum which was used to discern
structs, unions, and tagged unions, although the ImportVerilog
conversion never generated anything besides structs. Once we add support
for unions in the future, the intention is to define new types in ODS
for the unions and reuse the `StructMember`.
Operations defined through TableGen will use a version of type parsing
and printing that strips away the dialect prefix in case this does not
lead to ambiguities. If an op specifies a type like `UnpackedType`, the
generated parser and printer will call `UnpackedType::parse` and
`UnpackedType::print` in order to parse and print that type. This method
usually prints the type without any dialect prefixes, and often also
without the type name itself (as it is obvious given the type).
Add an implementation for `parse` and `print` to `UnpackedType` which
performs this stripped printing. This makes the assembly more compact
and in-line with what MLIR would generate by default if a
TableGen-specified op would use a TableGen-specified type.
This makes the integer flavor of `IntType` look exactly like the builtin
integer type, which will facilitate a future change from Moore's integer
type to the builtin integer. Parsing is unambiguous, since the stripped
form is only used when the type is clear from the op context.
Move the definitions of all array types from C++ land into
`MooreTypes.td`. This removes a significant amount of redundant code and
simplifies the dialect's type system.
Replace packed and unpacked ranges (`T [4:3]` or `T [2:4]`) with a new
type that discards the directionality and offset of the range. This
information is no longer needed at the IR level. Any meaning that the
offsets have can be encoded in the corresponding ops. Both ranges are
now represented as `array<2 x T>` and `array<3 x T>`, respectively.
Combine unpacked ranges (`T foo [6:2]`) and unpacked arrays
(`T foo [42]`) into a single `uarray<N x T>` type.
* Introduced new ltl ops
* added ops to visitor
* updated exportverilog
* added type inference for intersect
* updated tests
* added fold for trivial case
* Added FIRRTL intrinsics and test
* comments
* updated op requirements
LowerClasses creates an object for a corresponding instance only if the
instantiated module has property ports. But a class can be created for a
corresponding module based on other conditions like, if the module is public,
or instantiates other classes. This results in un-instantiated classes that
donot correspond to the module hierarchy.
This change ensures that if a class is created for a module, the object is also
created from the corresponding instance. Thus the module hierarchy is also
preserved in the om IR. Downstream tools parsing the IR can assume a single
top level class which is required for object model evaluation.
- Recursive source collection
- Run vlog on each file
- Run vlog in a Questa session to improve the speed
- Add no compile option
- Run vopt during compile so missing modules get reported
* [ImportVerilog] Support member-access expression
Support member-access expression.
Add container multiSymbolValue for multi-symbols pointing one value.
Signed-off-by: mingzheTerapines <mingzhe.zhang@terapines.com>
* [ImportVerilog] Support member-access expression
Separate two containers and their annotations.
* [ImportVerilog] Support member-access expression3
use auto instead of const slang::ast::Expression *
declare concatName with expr.member.name
* [ImportVerilog] Support member-access expression4
Simplfy string allocation.
* [ImportVerilog] Support member-access expression
The signing of unpacked structures is not allowed.- IEEE Standard
* [ImportVerilog] Support member-access expression6
Add packed unsigned struct occasion for testing.
* [ImportVerilog] Support Union Type
Support Union Type
Modify uniont tyep to event type as error type example.
* [ImportVerilog]Add errors example
Add error example for unpacked union.
* [ImportVerilog] Add strucfield op
Define a struct field access op that can represent accesses into struct fields.
* [ImportVerilog] Add struct inject and extract op
Add struct inject and extract op.
Remove union support.
* [ImportVerilog] Support memberaccess
* Removed some useless include.
* fix test error
* Fix errors.sv
* remove space.
---------
Signed-off-by: mingzheTerapines <mingzhe.zhang@terapines.com>
Now that invalid is better defined, we can start propagating it when we can preserver semantics. This means not breaking the one-op-is-one-consistent-value (e.g. not duplicating). The only bit mutating op which is touched by this change is not, which is a pure all-bits inversion, which should be safe (tm).
This converts wires into nodes when there is one write to the wire and it dominates the reads. By converting to nodes, this pass does not have to worry about symbols, references, or annotations. Those are just copied to the node.
This converts wires into nodes when there is one write to the wire and it dominates the reads. By converting to nodes, this pass does not have to worry about symbols, references, or annotations. Those are just copied to the node.
This PR fixes a regression caused by PortAnnotation mutation. We have to batch-update the port annotations to avoid compile time regression. Several other improves are added along with the fix:
* `shouldCreateClass` is slightly expensive since it walks entire IR to check instances. `shouldCreateClass` is already lazily evaluated but however `shouldCreateClass` is immediately called for every module. So this PR changes to compute the all results parallelly beforehand instead of lazy evaluation.
* `std::distance(a, b) == 0` is replaced with `a == b` to avoid potential iterator traversals (maybe it is optimized by clang/gcc though).
* `processPathTrackers` is refactored into a helper struct `PathTracker` so that we can process paths/annotations parallely. We update `pathInfoTable` sequentially afterwards.
* Several operation walks were replaced with instance graph traversal.
It should be NFC completely. Pass should behave exactly the same way.
Using the simulation environment was causing some applications to use
the shared objects distributed with the wheel. That's usually wrong
since the wheel shared objects are compiled with the "old" string C++
library for compatibility reasons. C++ applications which are compiled
against the ESI runtime don't use that.
Fix FoldUnusedPorts to use rewriter for RAUW.
Fix FoldReadWritePorts to use rewriter for RAUW.
Detected by -DMLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS=ON.
cc #7047.
Fix more RAUW's to use rewriter, inspection.
Retain logic to recognize (but not parse or diagnose) printf's
of the various "flavors" previously supported so that we can reject
designs that rely on this removed support (emit error).
mingzheTerapines