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Author SHA1 Message Date
Jack Koenig b4c7188413 Bump chisel3 
Summary of changes:
* Basic BundleLiteral support
* Add lit*Option methods for extracting literals
* Improved numbering of _T_*
* Undeprecate log2Up and log2Down
* BoringUtils for synthesizable cross module references
* Seq[Data] illegal in Bundle, override with ignoreSeq
* MixedVec
* Module Inlining and Flattening Support
* Verilog memory loading
* Access module ports via DataMirror.modulePorts
* Support for .B on [Big]Ints
* Stack Trace Trimming
* toBool[s] -> asBool[s]
* Improved UInt.-% emission
 2019-01-07 17:30:24 -08:00
Andrew Waterman e3a9ee30f2
Merge pull request #1761 from freechipsproject/fix-1752 
Move tvec bit-zapping from D to Q
 2019-01-03 17:19:30 -08:00
Srivatsa Yogendra 050f926f99
Merge pull request #1766 from freechipsproject/bump-riscv-tools-change 
bumping riscv-tools to spike change
 2019-01-02 14:50:02 -08:00
Srivatsa Yogendra e72d383930 bumping riscv-tools to spike change 2019-01-02 11:00:09 -08:00
Andrew Waterman b29af78096
Merge pull request #1763 from freechipsproject/pmp-rw 
Reserve the PMP R=0 W=1 combination
 2018-12-23 18:30:52 -08:00
Andrew Waterman 7f6b4c65ba Reserve the PMP R=0 W=1 combination 
This was a post-v1.10 amendment to the spec:

059f64c941
 2018-12-21 13:23:05 -08:00
Andrew Waterman e21266dc6a Move tvec bit-zapping from D to Q 
This addresses a simulation-pessimism problem.  The synthesis result
will be the same either way.  Before, in simulation, the value held in
these registers prior to the first write might not have had the
appropriate bits zapped, because of random initialization.

Resolves #1752
 2018-12-20 12:37:42 -08:00
Derek Pappas 18792a889d
fix getOMSubSystemComponents (#1745) 
* diamond-problem-fix
 2018-12-18 14:29:13 -08:00
Henry Cook af7545c356
tilelink: sram ecc notifications only on sram access (#1755) 2018-12-17 11:00:06 -08:00
Derek Pappas 4f0ca76fa5
fixing diamond problem (#1748) 2018-12-15 01:36:03 -08:00
Ryan Macdonald 4d8c68038a
Merge pull request #1740 from freechipsproject/trace-bundle-bridge 
Bundle bridge trace interface
 2018-12-14 16:28:29 -08:00
Ryan Macdonald ba59b3abf6 BundleBridge: Fix API bug 2018-12-14 13:45:25 -08:00
Ryan Macdonald ad7ce4797e Trace: Add directionality to trace bundle 2018-12-14 12:45:46 -08:00
Derek Pappas c60d724bbf
adding dcache om (#1754) 
* adding dcache om when there is no tim
 2018-12-14 12:33:34 -08:00
Jack Koenig e178d488fc
Bump firrtl, json4s, and sbt (#1739) 2018-12-13 18:45:10 -08:00
Ryan Macdonald 63c00973c1 Merge remote-tracking branch 'origin/master' into trace-bundle-bridge 2018-12-13 13:46:21 -08:00
Gleb Gagarin 6eac64c73a
Revert "Core monitor bundle (#1746)" (#1750) 
This reverts commit c69607cfd5.
 2018-12-12 20:18:51 -08:00
Andrew Waterman dd89f987cb
Merge pull request #1741 from freechipsproject/breakpoint-chain 
Implement debug trigger-sharing and chain-limiting proposals
 2018-12-11 16:32:54 -08:00
Ryan Macdonald 09e7bd410b Merge remote-tracking branch 'origin/master' into trace-bundle-bridge 2018-12-11 16:02:27 -08:00
Gleb Gagarin c69607cfd5
Core monitor bundle (#1746) 
* removed BundleMonitor
* moved CoreMonitorBundle class to package level
 2018-12-11 15:24:19 -08:00
Ryan Macdonald 621ee55f3f Trace: Use Broadcast node 2018-12-11 11:16:40 -08:00
Ryan Macdonald 42750089b3 Merge remote-tracking branch 'origin/master' into trace-bundle-bridge 2018-12-11 10:51:41 -08:00
Andrew Waterman ec67c4db03
Merge pull request #1743 from freechipsproject/killKnownRatio 
Provide a modicum of TL.A buffering in the NoCrossing case
 2018-12-10 17:01:12 -08:00
Andrew Waterman fa5770a28d Take advantage of breakpoint chain limit of 2 2018-12-10 15:17:01 -08:00
Andrew Waterman 7ee7e39d6a Handle AsynchronousCrossing case in DCache 2018-12-10 14:58:03 -08:00
Andrew Waterman 4494e9fb4b Provide a modicum of TL.A buffering in the NoCrossing case 
This prevents livelock in a multi-master system
 2018-12-10 14:47:01 -08:00
Andrew Waterman df8c8b214b Remove misnamed method knownRatio 2018-12-10 14:43:12 -08:00
Andrew Waterman 75c1fabf6a Pass ClockCrossingType into DCache; use it instead of knownRatio 2018-12-10 14:42:53 -08:00
Derek Pappas ee8a13b25a
fixes a dcache problem (#1742) 2018-12-09 22:40:49 -08:00
Derek Pappas a609f01046
adding dcache,icache,rocket (#1733) 
* adding dcache,icache,rocket, fpu, btb

* refactoring rockettile and adding helper methods to the OM* case classes

* icaches are now optional

* refactored the DCache and ICache OM code
 2018-12-09 15:55:34 -08:00
Andrew Waterman 8f9c42ed80 Implement debug trigger-sharing and chain-limiting proposals 
- Don't allow chain to be set if this trigger doesn't belong to D-mode
  but the next trigger does.

- Don't allow dmode to be set if the previous trigger doesn't belong
  to D-mode and has chain set.

- Don't allow chains longer than 2.
 2018-12-08 15:30:54 -08:00
Ryan Macdonald 70161085b7 Bundle bridge trace interface 2018-12-07 17:19:22 -08:00
Andrew Waterman dbfb1636ab
Merge pull request #1729 from freechipsproject/dcache-qor 
Remove a D$ ECC critical path
 2018-12-07 09:30:57 -08:00
Michael Maloney b50561d91e Fix URL in README.md in FPGA section. (#1734) 2018-12-05 21:22:34 -08:00
Derek Pappas 165a6f4866
added isa u spec (#1735) 2018-12-05 11:46:12 -08:00
Ernie Edgar 6532893798
Merge pull request #1715 from freechipsproject/debug-hart-arrays 
Added hart array feature
 2018-12-04 11:34:48 -07:00
Ernie Edgar 02df475ac1 Added hart array feature 2018-12-04 08:01:55 -08:00
Derek Pappas 29286d9d82
refactoring (#1732) 2018-12-03 19:43:08 -08:00
Derek Pappas bbbe91c2fc
new om for rams (#1731) 2018-12-03 12:45:40 -08:00
Wesley W. Terpstra 0c2664cebe
Merge pull request #1730 from freechipsproject/misc-fixes 
Fix a few issues with multi-chip designs
 2018-12-03 09:46:42 -10:00
Wesley W. Terpstra 6ba11a3159 AddressAdjuster: fix untested and broken code 2018-12-01 22:45:58 -08:00
Andrew Waterman 4e741ebf80 Pipeline D$ ECC -> tag-update path 
This actually saves hardware...
 2018-12-01 20:15:44 -08:00
Andrew Waterman 6d939b05a8 Inline the D$ arbiters 
These are always on the critical path, and inlining them provides
more opportunity to optimize the control paths in some flows.

Note this doesn't do anything useful without invoking the
firrtl InlineInstances transform.
 2018-12-01 17:34:21 -08:00
Andrew Waterman c00874c370 Remove a D$ ECC critical path introduced in 29954c6ffe 2018-12-01 17:33:49 -08:00
Henry Cook 7990d8ba1e
Merge pull request #1728 from freechipsproject/tile-output-interrupts 
Tile Notification Nodes
 2018-11-30 18:49:17 -08:00
Henry Cook c90a809f98 tlram: fix notify index bit width 2018-11-30 13:21:52 -08:00
Henry Cook 57255de6bc tilelink: ram can notify of ecc errors 2018-11-30 10:07:30 -08:00
Henry Cook 714155f2e9 ecc: add params case class 2018-11-30 10:06:58 -08:00
Derek Pappas 7292969bf9
Nomi5 (#1726) 
* adding getOMComponents to ports

* fixing formatting

* created a new getOMPortMemoryRegions

* cosmetic
 2018-11-30 08:37:41 -08:00
Henry Cook 1ec033af35 tile: all tiles have notification nodes 2018-11-29 12:38:32 -08:00