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Merge pull request #1741 from freechipsproject/breakpoint-chain 

Implement debug trigger-sharing and chain-limiting proposals
This commit is contained in:
Andrew Waterman 2018-12-11 16:32:54 -08:00 committed by GitHub
parent c69607cfd5 fa5770a28d
commit dd89f987cb
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 23 additions and 17 deletions
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12
src/main/scala/rocket/Breakpoint.scala
View File

@ -70,14 +70,14 @@ class BreakpointUnit(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
io.bp.foldLeft((Bool(true), Bool(true), Bool(true))) { case ((ri, wi, xi), bp) =>
val en = bp.control.enabled(io.status)
val r = en && ri && bp.control.r && bp.addressMatch(io.ea)
val w = en && wi && bp.control.w && bp.addressMatch(io.ea)
val x = en && xi && bp.control.x && bp.addressMatch(io.pc)
val r = en && bp.control.r && bp.addressMatch(io.ea)
val w = en && bp.control.w && bp.addressMatch(io.ea)
val x = en && bp.control.x && bp.addressMatch(io.pc)
val end = !bp.control.chain
when (end && r) { io.xcpt_ld := !bp.control.action; io.debug_ld := bp.control.action }
when (end && w) { io.xcpt_st := !bp.control.action; io.debug_st := bp.control.action }
when (end && x) { io.xcpt_if := !bp.control.action; io.debug_if := bp.control.action }
when (end && r && ri) { io.xcpt_ld := !bp.control.action; io.debug_ld := bp.control.action }
when (end && w && wi) { io.xcpt_st := !bp.control.action; io.debug_st := bp.control.action }
when (end && x && xi) { io.xcpt_if := !bp.control.action; io.debug_if := bp.control.action }
(end || r, end || w, end || x)
}

28
src/main/scala/rocket/CSR.scala
View File

@ -791,16 +791,23 @@ class CSRFile(
if (nBreakpoints > 0) {
when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata }
val bp = reg_bp(reg_tselect)
when (!bp.control.dmode || reg_debug) {
when (decoded_addr(CSRs.tdata1)) {
val newBPC = new BPControl().fromBits(wdata)
val dMode = newBPC.dmode && reg_debug
bp.control := newBPC
bp.control.dmode := dMode
bp.control.action := dMode && newBPC.action
for ((bp, i) <- reg_bp.zipWithIndex) {
when (i === reg_tselect && (!bp.control.dmode || reg_debug)) {
when (decoded_addr(CSRs.tdata2)) { bp.address := wdata }
when (decoded_addr(CSRs.tdata1)) {
bp.control := wdata.asTypeOf(bp.control)
val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain
val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode
val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain
val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode
val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control)
val dMode = newBPC.dmode && reg_debug && (prevDMode || !prevChain)
bp.control.dmode := dMode
bp.control.action := dMode && newBPC.action
bp.control.chain := newBPC.chain && !(prevChain || nextChain) && (dMode || !nextDMode)
}
}
when (decoded_addr(CSRs.tdata2)) { bp.address := wdata }
}
}
if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)) zipWithIndex) {
@ -837,8 +844,6 @@ class CSRFile(
reg_satp.asid := 0
if (nBreakpoints <= 1) reg_tselect := 0
if (nBreakpoints >= 1)
reg_bp(nBreakpoints-1).control.chain := false
for (bpc <- reg_bp map {_.control}) {
bpc.ttype := bpc.tType
bpc.maskmax := bpc.maskMax
@ -851,6 +856,7 @@ class CSRFile(
when (reset) {
bpc.action := false
bpc.dmode := false
bpc.chain := false
bpc.r := false
bpc.w := false
bpc.x := false