3ba15f82c4
Reduce delay between ECC and s2_nack/resp.valid
2019-01-31 12:06:42 -08:00
8ef996aff0
Improve D$ ECC QoR by removing post-ECC word mux
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It is instead merged into the way mux.
2019-01-31 12:06:42 -08:00
e1b4f5ad37
Replace toBool(s) with asBool(s) ( #1809 )
2019-01-30 18:44:51 -08:00
84252d2445
Om scala plic fix1 ( #1800 )
2019-01-30 12:03:29 -08:00
aba5773441
Merge pull request #1806 from freechipsproject/pmp-reset
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Encapsulate PMP reset
2019-01-29 20:32:53 -08:00
c3bdbd8ada
add docname ( #1802 )
2019-01-29 11:31:33 -08:00
9a0f4df75a
Merge pull request #1808 from freechipsproject/bump_riscv_tools_for_spike_fix
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Bumping riscv-tools
2019-01-29 10:00:07 -08:00
3e7beb866d
bumping riscv-tools
2019-01-28 17:44:20 -08:00
d859a1c048
Encapsulate PMP reset
2019-01-28 13:42:37 -08:00
e86a4df663
Support delegation of misaligned ld/st and illegal instruction traps ( #1799 )
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This facilitates moving emulation code out of the M-mode trusted codebase.
2019-01-25 11:15:54 -08:00
b4f732fc9f
subsystem: add a fragmenter to tile slave port bus blocker control ( #1801 )
2019-01-24 19:19:23 -08:00
1d947b6653
* Added HasCoreMonitor trait to HasTiles trait ( #1797 )
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* Moved CoreMonitorBundle class to util package
2019-01-22 14:22:26 -08:00
8eec2204cf
Debug interface ( #1794 )
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* adding cjtag
2019-01-21 16:41:36 -08:00
c15bfe49d5
remove require from ECCParams ( #1792 )
2019-01-21 10:08:44 -08:00
b9b95f493a
adding missing type ( #1791 )
2019-01-18 23:33:12 -08:00
fb5ac38480
added per channel BufferParams case classes for TL, AXI4 ( #1787 )
2019-01-18 11:08:07 -08:00
4b37841872
Relax assertion in Debug.scala, allow dmactive to be used to exit from busy state in DM ( #1782 )
2019-01-17 10:19:13 -08:00
68380eb9c3
Merge pull request #1784 from freechipsproject/seip-clock-gate
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Respect SEIP during WFI clock gate
2019-01-17 10:02:08 -08:00
508dd91184
Merge pull request #1783 from freechipsproject/fuzzing-plusarg
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rename ahb_fuzzing plusarg
2019-01-17 09:33:44 -08:00
d79cd12252
Avoid excess tag write after flush
2019-01-17 02:34:27 -08:00
976a8aa163
Respect SEIP during WFI clock gate
2019-01-16 22:47:34 -08:00
c1c3f7356c
rename ahb_fuzzing plusarg
2019-01-16 17:21:22 -08:00
e0c622cc50
Merge pull request #1781 from freechipsproject/fuzzing-plusarg
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Add plusarg option to disable fuzzing
2019-01-16 15:23:54 -08:00
e9aa5c5123
adding om registers ( #1773 )
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* adding registers to the OM
2019-01-16 11:17:20 -08:00
0b57334e18
Add plusarg option to disable fuzzing
2019-01-16 10:18:53 -08:00
772a8a475d
AXI4Fragmenter: splitting up bursts impacts the inflight transactions ( #1780 )
2019-01-15 20:05:50 -08:00
6bbcf622a3
Merge pull request #1776 from freechipsproject/qor
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Minor QoR improvements
2019-01-15 16:59:47 -08:00
79c3d9880a
Fix typo in fragmented-superpage handling code
2019-01-15 14:46:33 -08:00
c76bb44e32
Move getomcomponents1 ( #1772 )
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* changing where getOMComponents is called in the flow
2019-01-15 11:11:47 -08:00
a9a90afd6b
Minor D$ QoR improvement
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s2_xcpt doesn't need to drive so many things.
2019-01-11 22:27:41 -08:00
ad61beed8a
Merge pull request #1775 from freechipsproject/trace-node-name
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Trace: suggestName trace node
2019-01-11 17:47:27 -08:00
af7d05ce9b
Trace: suggestName trace node
2019-01-11 13:25:12 -08:00
89637f6945
Merge pull request #1770 from freechipsproject/bump-chisel
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Bump chisel3
2019-01-08 12:48:44 -08:00
b4c7188413
Bump chisel3
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Summary of changes:
* Basic BundleLiteral support
* Add lit*Option methods for extracting literals
* Improved numbering of _T_*
* Undeprecate log2Up and log2Down
* BoringUtils for synthesizable cross module references
* Seq[Data] illegal in Bundle, override with ignoreSeq
* MixedVec
* Module Inlining and Flattening Support
* Verilog memory loading
* Access module ports via DataMirror.modulePorts
* Support for .B on [Big]Ints
* Stack Trace Trimming
* toBool[s] -> asBool[s]
* Improved UInt.-% emission
2019-01-07 17:30:24 -08:00
e3a9ee30f2
Merge pull request #1761 from freechipsproject/fix-1752
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Move tvec bit-zapping from D to Q
2019-01-03 17:19:30 -08:00
050f926f99
Merge pull request #1766 from freechipsproject/bump-riscv-tools-change
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bumping riscv-tools to spike change
2019-01-02 14:50:02 -08:00
e72d383930
bumping riscv-tools to spike change
2019-01-02 11:00:09 -08:00
b29af78096
Merge pull request #1763 from freechipsproject/pmp-rw
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Reserve the PMP R=0 W=1 combination
2018-12-23 18:30:52 -08:00
7f6b4c65ba
Reserve the PMP R=0 W=1 combination
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This was a post-v1.10 amendment to the spec:
059f64c941
2018-12-21 13:23:05 -08:00
e21266dc6a
Move tvec bit-zapping from D to Q
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This addresses a simulation-pessimism problem. The synthesis result
will be the same either way. Before, in simulation, the value held in
these registers prior to the first write might not have had the
appropriate bits zapped, because of random initialization.
Resolves #1752
2018-12-20 12:37:42 -08:00
18792a889d
fix getOMSubSystemComponents ( #1745 )
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* diamond-problem-fix
2018-12-18 14:29:13 -08:00
af7545c356
tilelink: sram ecc notifications only on sram access ( #1755 )
2018-12-17 11:00:06 -08:00
4f0ca76fa5
fixing diamond problem ( #1748 )
2018-12-15 01:36:03 -08:00
4d8c68038a
Merge pull request #1740 from freechipsproject/trace-bundle-bridge
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Bundle bridge trace interface
2018-12-14 16:28:29 -08:00
ba59b3abf6
BundleBridge: Fix API bug
2018-12-14 13:45:25 -08:00
ad7ce4797e
Trace: Add directionality to trace bundle
2018-12-14 12:45:46 -08:00
c60d724bbf
adding dcache om ( #1754 )
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* adding dcache om when there is no tim
2018-12-14 12:33:34 -08:00
e178d488fc
Bump firrtl, json4s, and sbt ( #1739 )
2018-12-13 18:45:10 -08:00
63c00973c1
Merge remote-tracking branch 'origin/master' into trace-bundle-bridge
2018-12-13 13:46:21 -08:00
6eac64c73a
Revert "Core monitor bundle ( #1746 )" ( #1750 )
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This reverts commit c69607cfd5
2018-12-12 20:18:51 -08:00
Andrew Waterman