2019-03-09 08:23:35 +08:00
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#########################################################################################
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# makefile variables shared across multiple makefiles
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#########################################################################################
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#########################################################################################
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2019-04-22 05:41:02 +08:00
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# default variables to invoke the generator for a example Rocket system
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2019-03-09 08:23:35 +08:00
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# descriptions:
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2019-04-18 07:06:42 +08:00
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# PROJECT = the scala package to find the MODEL/Generator in
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2019-04-23 13:36:04 +08:00
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# MODEL = the top level module of the project in Chisel (normally the harness)
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2019-04-23 14:26:13 +08:00
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# VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness)
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2019-03-09 08:23:35 +08:00
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# CONFIG = the configuration class to give the parameters for the project
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# CFG_PROJECT = the scala package to find the CONFIG class
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2019-03-09 10:20:42 +08:00
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# SBT_PROJECT = the SBT project that you should find the Generator class in
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# TB = wrapper over the TestHarness needed to simulate in VCS
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# TOP = top level module of the project (normally the module instantiated by the harness)
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2019-04-18 08:52:31 +08:00
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#
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# project specific:
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# SUB_PROJECT = use the specific subproject default variables
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#########################################################################################
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PROJECT ?= example
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MODEL ?= RocketTestHarness
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VLOG_MODEL ?= TestHarness
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CONFIG ?= DefaultRocketConfig
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CFG_PROJECT ?= $(PROJECT)
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SBT_PROJECT ?= $(PROJECT)
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TB ?= TestDriver
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TOP ?= RocketTop
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2019-03-09 08:23:35 +08:00
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2019-04-24 09:34:42 +08:00
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#########################################################################################
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# subproject overrides
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# description:
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# - make it so that you only change 1 param to change most or all of them!
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# - mainly intended for quick developer setup for common flags
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# - for each you only need to specify a CONFIG
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#########################################################################################
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SUB_PROJECT ?= example
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# for a BOOM based example system
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ifeq ($(SUB_PROJECT),boomexample)
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MODEL=BoomTestHarness
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TOP=BoomTop
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endif
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# for BOOM developers
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ifeq ($(SUB_PROJECT),boom)
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PROJECT=boom.system
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MODEL=TestHarness
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CFG_PROJECT=boom.system
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SBT_PROJECT=boom
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TOP=ExampleBoomSystem
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endif
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# for Rocket-chip developers
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ifeq ($(SUB_PROJECT),rocketchip)
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PROJECT=freechips.rocketchip.system
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MODEL=TestHarness
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CFG_PROJECT=freechips.rocketchip.system
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SBT_PROJECT=rebarrocketchip
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TOP=ExampleRocketSystem
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endif
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# for Hwacha developers
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ifeq ($(SUB_PROJECT),hwacha)
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PROJECT=freechips.rocketchip.system
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MODEL=TestHarness
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CFG_PROJECT=hwacha
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SBT_PROJECT=hwacha
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TOP=ExampleRocketSystem
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TB=TestDriver
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endif
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2019-03-09 08:23:35 +08:00
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#########################################################################################
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# path to rocket-chip and testchipip
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#########################################################################################
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2019-04-19 02:39:19 +08:00
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ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip
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TESTCHIP_DIR = $(base_dir)/generators/testchipip
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REBAR_FIRRTL_DIR = $(base_dir)/tools/firrtl
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2019-03-09 08:23:35 +08:00
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#########################################################################################
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# names of various files needed to compile and run things
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#########################################################################################
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long_name = $(PROJECT).$(MODEL).$(CONFIG)
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# if building from rocketchip, override the long_name to match what they expect
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ifeq ($(PROJECT),freechips.rocketchip.system)
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long_name=$(CFG_PROJECT).$(CONFIG)
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endif
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FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
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ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
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VERILOG_FILE ?= $(build_dir)/$(long_name).top.v
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2019-04-18 07:02:44 +08:00
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TOP_FIR ?= $(build_dir)/$(long_name).top.fir
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TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json
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HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v
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HARNESS_FIR ?= $(build_dir)/$(long_name).harness.fir
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HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json
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SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v
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SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf
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SMEMS_FIR ?= $(build_dir)/$(long_name).mems.fir
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sim_dotf ?= $(build_dir)/sim_files.f
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2019-04-18 07:02:44 +08:00
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sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
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sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f
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2019-03-09 08:23:35 +08:00
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#########################################################################################
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# default sbt launch command
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#########################################################################################
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SCALA_VERSION=2.12.4
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SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION))
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SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION)
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#########################################################################################
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# output directory for tests
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#########################################################################################
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output_dir=$(sim_dir)/output
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#########################################################################################
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# build output directory for compilation
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#########################################################################################
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build_dir=$(sim_dir)/generated-src
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#########################################################################################
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# vsrcs needed to run projects
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#########################################################################################
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rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
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#########################################################################################
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# sources needed to run simulators
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#########################################################################################
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sim_vsrcs = \
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$(VERILOG_FILE) \
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$(HARNESS_FILE) \
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$(SMEMS_FILE)
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#########################################################################################
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# assembly/benchmark variables
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#########################################################################################
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timeout_cycles = 10000000
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bmark_timeout_cycles = 100000000
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